Hardware

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Home * Hardware

Basics

Special Purpose Hardware

Dedicated Chess Hardware

Programmable Logics

PAL - Programmable array logic
GAL - Generic array logic
CPLD - Complex programmable Logic Device
FPGA - Field-programmable gate array

Famous Chess Machines

General Purpose Hardware

Historic Computers

Mainframes

Amdahl

Amdahl 470

CDC

Cray

Honeywell

Honeywell 6000 (GE-600)

IBM

ICL ...

PDP

PDP-6
PDP-10

Siemens/Fujitsu

Siemens-System 7.800

TR

TR-4
TR 440

UNIVAC

Massively Parallel

Minis & Workstations

Single Board Computers

Home Computers

Home- and Personal Computers

Acorn Computers Ltd

Acorn Archimedes

Atari 8-bit

Commodore PET

Commodore VIC-20

TRS-80

Mobile Computers

Mobile phone

µ-Processors & Controller

PIC Microcontroller

8-bit

16-bit

32-bit

x86 by Intel and AMD
68000 by Motorola (external 16 bit databus)
68020 by Motorola
68030 by Motorola
ARM2 by Acorn Computers Ltd
ARM6 by Advanced RISC Machines Ltd
ARM11 by Advanced RISC Machines Ltd
PowerPC by Apple, IBM and Motorola
SPARC V7/V8 by Sun Microsystems

Transputer

T800 by Inmos

64-bit

DEC Alpha by Digital Equipment Corporation
i860 by Intel
Itanium by Intel
x86-64 or x64 by AMD and Intel
PowerPC 620 by Apple, IBM and Motorola
PowerPC G5 by IBM
SPARC V9 by Sun Microsystems

Misc

Publications

1960 ...

Martin H. Weik (1961). A Third Survey of Domestic Electronic Digital Computing Systems. Report No. 1115

1970 ...

Gordon Bell, Allen Newell (1971). Computer Structures: Readings and Examples. McGraw-Hill, ISBN-13: 978-0070043572, amazon
Ozalp Babaoglu (1977). Hardware implementation of the legal move generation and relative ordering functions for the game of chess. Master's thesis, University of California, Berkeley
John Moussouris, Jack Holloway, Richard Greenblatt (1979). CHEOPS: A Chess-orientated Processing System. Machine Intelligence 9 (Jean Hayes Michie, Donald Michie and L.I. Mikulich editors) Ellis Horwood, Chichester, 1979, pp. 351-360. Reprinted (1988) in Computer Chess Compendium » CHEOPS

1980 ...

Joe Condon, Ken Thompson (1982). Belle Chess Hardware. Advances in Computer Chess 3, Reprinted (1988) in Computer Chess Compendium » Belle
Carl Ebeling, Andrew James Palay (1984). The Design and Implementation of a VLSI Chess Move Generator. Proceedings of the 11th Annual International Symposium on Computer Architecture. IEEE and ACM.
Carl Ebeling (1986). All the Right Moves: A VLSI Architecture for Chess. Ph.D. thesis, Carnegie Mellon University, MIT Press, ISBN 0-262-05035-8, amazon.com ^[1] » HiTech
Feng-hsiung Hsu (1986). Two designs of functional units for VLSI based chess machines. Carnegie Mellon University, Computer Science Department. Paper 1566. » ChipTest
Feng-hsiung Hsu (1987). A Two-Million Moves/Sec CMOS Single-Chip Chess Move Generator. IEEE J. of Solid-state Circuits, Vol. 22, No. 5, pp. 841-846.

1990 ...

James Testa, Alvin M. Despain (1990). A CMOS VLSI chess microprocessor. University of California, Berkeley, IEEE Custom Integrated Circuit Conference
Feng-hsiung Hsu, Murray Campbell, Joe Hoane (1995). Deep Blue System Overview. International Conference on Supercomputing, 1995: 240-244 » Deep Blue
Yi-Fan Ke (1996). A parallel hardware architecture for accelerating computer chess system-平行電腦象棋系統架構之設計及研究. Ph.D. thesis, National Taiwan University
Yi-Fan Ke, Tai-Ming Parng (1996). A Parallel Hardware Architecture for Accelerating α-β Game Tree. IEICE Transactions on Information and Systems, September, 1996, pp. 1232-1240
Feng-hsiung Hsu (1999). IBM’s Deep Blue Chess Grandmaster Chips. IEEE Micro, Vol. 19, No. 2 (Mar-Apr), pp. 70-81. ISSN 0272-1732. pdf

2000 ...

Marc Boulé (2002). An FPGA Move Generator for the Game of Chess. Masters thesis, McGill University, (Supervisor: Zeljko Zilic, Co-Supervisor: Monty Newborn), pdf
Marc Boulé, Zeljko Zilic (2002). An FPGA Move Generator for the Game of Chess. ICGA Journal, Vol. 25, No. 2, pdf
Chrilly Donninger, Ulf Lorenz (2004). The Chess Monster Hydra in Field Programmable Logic and Application, 14th International Conference, FPL 2004, Leuven, Belgium, August 30-September 1, 2004. Proceedings, pp 927-932. Springer Berlin / Heidelberg, ISBN 978-3-540-22989-6, pdf
Samuel T. King, Joseph Tucek, Anthony Cozzie, Chris Grier, Weihang Jiang, Yuanyuan Zhou (2008). Designing and Implementing Malicious Hardware. LEET 2008, pdf

Forum Posts

Computer chess and processor speed in 20 years from now... by Chris, CCC, February 26, 2003
hardware advances - a different perspective by Robert Hyatt, CCC, September 09, 2010
old crafty vs new crafty on new hardware by Robert Hyatt, CCC, September 11, 2010 » Knowledge, Crafty
Final results - Crafty - hardware vs software by Robert Hyatt, CCC, September 13, 2010 » Software, Crafty
hardware doubling number for Crafty by Robert Hyatt, CCC, September 15, 2010 » Crafty
Good question: What % improvement is hardware vs. software? by Jonathan Lee, CCC, January 17, 2014
Moore's Law by Mark Lefler, CCC, March 16, 2016 ^[2] ^[3]
The Gigatron project by Harm Geert Muller, CCC, December 06, 2017 » Gigatron

External Links

References

↑ Any opinion about this book?: "All the Right Moves" by E Diaz, CCC, January 02, 2012
↑ Moore's law from Wikipedia
↑ After Moore's law | Technology Quarterly | The Economist, March 12, 2016
↑ Moore's Law by Mark Lefler, CCC, March 16, 2016
↑ The Gigatron project by Harm Geert Muller, CCC, December 06, 2017

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