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Die shot of Intel 80386 DX-25 [1]

referring the IA-32 architecture of the 32-bit instruction set of the Intel 80386 processor released in 1985 - the successor of Intel's 16-bit 8086 until 80286 processors. x86-32 could address up to 4GByte physical memory, had virtual memory pages and a mode to protect them over process boundaries - a requirement for multitasking operating systems, despite 16-bit MS-DOS was still popular. While the initial x86 was Complex Instruction Set Computing (CISC), the RISC versus CISC issue had become indistinct with more recent x86 processors, internally processing RISC like micro opcode. Over the time, modern architectural features, such as Out-of-order execution, Pipelining, Register Renaming and Branch Predication became an issue. 80386 was once clocked by about 25MHz. The RAM access speed could not keep up with higher and higher clock frequency of later processors - small but faster cache memory became necessary and strategies to make them efficient, nowadays even with three cache levels with different size and speed.

see x86-64 for x86 64-bit

Computer Chess

A lot of commercial and amateur PC chess programs, notably under the operating systems MS-DOS and later Windows and Linux, were developed for this widespread architecture, often taking advantage of 32-bit registers and new instructions, for instance bsf and btr for bitscanning 2 * 32-bit Bitboards and 32-bit Piece-Sets. Those instructions were usually not available through high level programming languages, but through Assembly language, later often as inline assembly of various high level language compilers, for instance Microsoft Visual C and the GNU C Compiler. Under the 16-bit real mode operating system MS-DOS, it was quite common in chess programming to use the unreal mode [2] [3] to allocate much more physical memory for the Transposition Table, the 16 bit operating system, not aware of the huge address space, could access. Other DOS programs relied on memory extenders.


While the 80386 represented the third microarchitecture (after 8086, 80286), 80486 and Pentium were the fourth and fifth, later called P5 microarchitecture. In 1995 with Pentium Pro, Intel introduced the P6 microarchitecture, eventually revived in the Pentium M line of microprocessors and the predecessor of Intel's Core 2 microarchitecture. Intel's NetBurst microarchitecture with the advent of the Pentium 4 processor, was famous for its clock speed, but no good reputation by most chess programmers, who favored the AMD K6- and K7-architecture, namely the Athlon processor at that time. To begin with the rebirth of P6 and Intel Core 2 architecture in 2006, things changed in favor to Intel again. In November 2008 the Nehalem microarchitecture appeared.

Intel's IA-64 architecture is a complete new and incompatible instruction set to IA-32. It is used by the Itanium line of processors. The backward compatible 64-bit successor was designed by AMD with the advent of Hammer or AMD64, later cloned by Intel and together referred to the x86-64 architecture.

Register Files

x86 has eight 32-bit general purpose registers:

General Purpose

The eight general purpose registers may be treated as 32-bit Double Word, 16-bit Word and high and low Byte:

32 16 8 high 8 low Purpose
EAX AX AH AL GP, Accumulator
EBX BX BH BL GP, Index Register
ECX CX CH CL GP, Counter, variable shift, rotate via CL
EDX DX DH DL GP, high Accumulator mul/div
ESI SI - - GP, Source Index
EDI DI - - GP, Destination Index
ESP SP - - Stack Pointer
EBP BP - - GP, Base Pointer


MMX was introduced with Pentium MMX in 1996, adopted by AMD's K6 in 1997. Eight 64-bit MMX-Registers: MM0 - MM7. Treated as Double or Quad Word, vector of two Floats or Double Words, and as vector if four Words or eight Bytes.


An MMX-floating point extension by AMD, introduced in the K6-2 processor, 1998. It uses the eight 64-bit MMX-Registers: MM0 - MM7.


SSE was introduced by Pentium III in 1997, SSE2 by Pentium 4 in 2000 Eight 128-bit XMM-Registers: XMM0 - XMM7. Treated as vector of two Doubles (SSE) or Quad Words (SSE2), as vector of four Floats (SSE) or Double Words (SSE2), and as vector if eight Words (SSE2) or 16 Bytes (SSE2).



Pentium with P54C core [4]



AMD Athlon XP (Thoroughbred) [5]
AMD has continued the name with the Athlon 64, featuring AMD64 64-bit technology, later called x86-64.


Operating Systems









Forum Posts

External Links



Instruction Sets


Security Vulnerability


  1. Die shot of Intel 80386 DX-25 microprocessor (SX215) by Pauli Rautakorpi, October 28, 2013, Wikimedia Commons
  2. Flat real / real big / unreal mode (v1.2) from Programmer's Heaven
  3. Unreal mode by Safronov's family, comp.lang.asm.x86, June 5, 2003
  4. Die shot of Intel Pentium with P54C core by Pauli Rautakorpi, June 11, 2013, Wikimedia Commons
  5. Die shot of AMD Athlon XP microprocessor with Thoroughbred core (AXDA1800DLT3C) by Pauli Rautakorpi, February 14, 2014, Wikimedia Commons

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