Sequential Logic

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Sequential circuit [1]

A Sequential Logic is a digital circuit where one or more outputs are boolean functions of multiple inputs and the history of the outputs. In contrast to combinatorial logic, a sequential logic requires memory to somehow feed the history of the outputs back to the inputs. Usually, for deterministic and reliable behavior considering internal latencies and propagation delays, a sequential logic is synchronous, that is the memory only change their content on the edge of a clock signal.


Sequential logic, that is combinatorial logic combined with memory, is the base of Finite-state machines, Turing machines as well as digital computers.

Sequential Rook Attack

As an further example, a sequential logic may perform the same task as mentioned in Combinatorial Attack and Defend Map, but with less gates in up to seven cycles - similar to the bitboard techniques like Dumb7Fill:

                                +------+     |       |
 o--/64/-- empty(square) -/64/--| 64:1 |---->|       |-----o result reliable / otherwise processing after reset
                                +------+     | Comb. |-----o A8 is attacked by white rook from south
                                   ^         | Logic |
                                +------+     |       |
 o--/64/-- wrook(square) -/64/--| 64:1 |---->|       |-->--+
                                +-----.+     |       |     |
                                   ^      o->|       |     |
                                 /6|      |  +-------+     |
                                   |      |                v
                                +--------------+           |
                                |              |           |
                                |    Latch     |<----------+
                     reset o----|              |

See also


  • Alan H. Bond (1987). Broadcasting Arrays - A Highly Parallel Computer Architecture Suitable For Easy Fabrication. pdf
  • Alan Clements (2005). Sequential Logic. pdf

External Links

Linear-feedback shift register from Wikipedia
Cyclic redundancy check from Wikipedia
1976 lineup: Klaus Doldinger, Curt Cress, Wolfgang Schmid, Kristian Schultze


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