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SuperSPARC II [1]

SPARC, (Scalable Processor Architecture)
a RISC architecture developed by Sun Microsystems introduced in 1986 as 32-bit and early 90s as 64-bit SMP architecture. Implementations of the original 32-bit SPARC V7 architecture were initially designed and used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68020 series of processors. Later UltraSPARC processors implementing the SPARC V9 architecture were used in SMP and ccNUMA servers and designed for 64-bit operations. Oracle continued the development of the SPARC V9 architecture after its acquisition of Sun, as recently with the Sparc M7 [2] [3].


The SPARC processor usually contains as many as 160 general purpose registers, with 32 of them immediately visible to software, that is 8 global register g0-g7 and 3x8 as register window at function entry and exit moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the adjacent windows to pass parameters or return values [4]. The endianness of the 32-bit SPARC V8 architecture is purely big-endian, while the 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian order, chosen either at the application instruction (load/store) level or at the memory page level (via an MMU setting) [5]. In 1995, the V9 UltraSPARC first implemented the SIMD Visual Instruction Set (VSI), introduced in 1994.

Chess Programs

SPARC Unix workstations were popular systems to run computer chess programs in the 90s, such as Ferret and DarkThought. Kasparov Sparc by Saitek was the last chess computer programmed by Kathe and Dan Spracklen [6]. The parallel MIT chess programs StarTech and *Socrates ran on NCSA's CM-5 with 512 SuperSPARC cores [7].

See also

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