GPU (Graphics Processing Unit),
a specialized processor primarily intended to fast image processing. GPUs may have more raw computing power than general purpose CPUs but need a specialized and parallelized way of programming. Leela Chess Zero has proven that a Best-first Monte-Carlo Tree Search (MCTS) with deep learning methodology will work with GPU architectures.
- 1 History
- 2 GPU in Computer Chess
- 3 GPU Chess Engines
- 4 GPGPU
- 5 Hardware Model
- 6 Programming Model
- 7 Memory Model
- 8 Instruction Throughput
- 9 Tensors
- 10 Host-Device Latencies
- 11 Deep Learning
- 12 Architectures
- 12.1 AMD
- 12.2 Apple
- 12.3 ARM
- 12.4 Intel
- 12.5 Nvidia
- 12.6 PowerVR
- 12.7 Qualcomm
- 12.8 Vivante Corporation
- 13 See also
- 14 Publications
- 15 Forum Posts
- 16 External Links
- 17 References
In the 1970s and 1980s RAM was expensive and Home Computers used custom graphics chips to operate directly on registers/memory without a dedicated frame buffer resp. texture buffer, like TIAin the Atari VCS gaming system, GTIA+ANTIC in the Atari 400/800 series, or Denise+Agnus in the Commodore Amiga series. The 1990s would make 3D graphics and 3D modeling more popular, especially for video games. Cards specifically designed to accelerate 3D math, such as the 3dfx Voodoo2, were used by the video game community to play 3D graphics. Some game engines could use instead the SIMD-capabilities of CPUs such as the Intel MMX instruction set or AMD's 3DNow! for real-time rendering. Sony's 3D capable chip used in the PlayStation (1994) and Nvidia's 2D/3D combi chips like NV1 (1995) coined the term GPU for 3D graphics hardware acceleration. With the advent of the unified shader architecture, like in Nvidia Tesla (2006), ATI/AMD TeraScale (2007) or Intel GMA X3000 (2006), GPGPU frameworks like CUDA and OpenCL emerged and gained in popularity.
GPU in Computer Chess
There are in main three approaches how to use a GPU for Chess:
- As an accelerator in Lc0: run a neural network for position evaluation on GPU.
- Offload the search in Zeta: run a parallel game tree search with move generation and position evaluation on GPU.
- As an hybrid in perft_gpu: expand the game tree to a certain degree on CPU and offload to GPU to compute the sub-tree.
GPU Chess Engines
Early efforts to leverage a GPU for general-purpose computing required reformulating computational problems in terms of graphics primitives via graphics APIs like OpenGL or DirextX, followed by first GPGPU frameworks such as Sh/RapidMind or Brook and finally CUDA and OpenCL.
- AMD OpenCL Developer Community
- ROCm Homepage
- AMD OpenCL Programming Guide
- AMD OpenCL Optimization Guide
- RDNA Instruction Set
- Vega Instruction Set
- Apple OpenCL Developer
- Apple Metal Developer
- Apple Metal Programming Guide
- Metal Shading Language Specification
- Nvidia CUDA Zone
- Nvidia PTX ISA
- Nvidia CUDA Toolkit Documentation
- Nvidia CUDA C++ Programming Guide
- Nvidia CUDA C++ Best Practices Guide
- C++ AMP (Microsoft)
- DirectCompute (Microsoft)
- OpenACC (offload directives)
- OpenMP (offload directives)
A common scheme on GPUs with unified shader architecture is to run multiple threads in SIMT fashion and a multitude of SIMT waves on the same SIMD unit to hide memory latencies. Multiple processing elements (GPU cores) are members of a SIMD unit, multiple SIMD units are coupled to a compute unit, with up to hundreds of compute units present on a discrete GPU. The actual SIMD units may have architecture dependent different numbers of cores (SIMD8, SIMD16, SIMD32), and different computation abilities - floating-point and/or integer with specific bit-width of the FPU/ALU and registers. There is a difference between a vector-processor with variable bit-width and SIMD units with fix bit-width cores. Different architecture white papers from different vendors leave room for speculation about the concrete underlying hardware implementation and the concrete classification as hardware architecture. Scalar units present in the compute unit perform special functions the SIMD units are not capable of and MMAC units (matrix-multiply-accumulate units) are used to speed up neural networks further.
|AMD Terminology||Nvidia Terminology|
|Compute Unit||Streaming Multiprocessor|
|Stream Core||CUDA Core|
- 512 CUDA cores @1.544GHz
- 16 SMs - Streaming Multiprocessors
- organized in 2x16 CUDA cores per SM
- Warp size of 32 threads
- 2048 Stream cores @0.925GHz
- 32 Compute Units
- organized in 4xSIMD16, each SIMT4, per Compute Unit
- Wavefront size of 64 work-items
Wavefront and Warp
Generalized the definition of the Wavefront and Warp size is the amount of threads executed in SIMT fashion on a GPU with unified shader architecture.
A parallel programming model for GPGPU can be data-parallel, task-parallel, a mixture of both, or with libraries and offload-directives also implicitly-parallel. Single GPU threads (work-items in OpenCL) contain the kernel to be computed and are coupled to a work-group, one or multiple work-groups form the NDRange to be executed on the GPU device. The members of a work-group execute the same kernel, can be usually synchronized and have access to the same scratch-pad memory, with an architecture limit of how many work-items a work-group can hold and how many threads can run in total concurrently on the device.
|OpenCL Terminology||CUDA Terminology|
|Compute Unit||Streaming Multiprocessor|
|Processing Element||CUDA Core|
Nvidia GeForce GTX 580 (Fermi, CC2) 
- Warp size: 32
- Maximum number of threads per block: 1024
- Maximum number of resident blocks per multiprocessor: 32
- Maximum number of resident warps per multiprocessor: 64
- Maximum number of resident threads per multiprocessor: 2048
AMD Radeon HD 7970 (GCN) 
- Wavefront size: 64
- Maximum number of work-items per work-group: 1024
- Maximum number of work-groups per compute unit: 40
- Maximum number of Wavefronts per compute unit: 40
- Maximum number of work-items per compute unit: 2560
OpenCL offers the following memory model for the programmer:
- __private - usually registers, accessable only by a single work-item resp. thread.
- __local - scratch-pad memory shared across work-items of a work-group resp. threads of block.
- __constant - read-only memory.
- __global - usually VRAM, accessable by all work-items resp. threads.
|OpenCL Terminology||CUDA Terminology|
|Local Memory||Shared Memory|
|Constant Memory||Constant Memory|
|Global Memory||Global Memory|
- 128 KiB private memory per compute unit
- 48 KiB (16 KiB) local memory per compute unit (configurable)
- 64 KiB constant memory
- 8 KiB constant cache per compute unit
- 16 KiB (48 KiB) L1 cache per compute unit (configurable)
- 768 KiB L2 cache
- 1.5 GiB to 3 GiB global memory
- 256 KiB private memory per compute unit
- 64 KiB local memory per compute unit
- 64 KiB constant memory
- 16 KiB constant cache per four compute units
- 16 KiB L1 cache per compute unit
- 768 KiB L2 cache
- 3 GiB to 6 GiB global memory
Usually data has to be copied between a CPU host and a discrete GPU device, but different architectures from different vendors with different frameworks on different operating systems may offer a unified and accessible address space between CPU and GPU.
GPUs are used in HPC environments because of their good FLOP/Watt ratio. The instruction throughput in general depends on the architecture (like Nvidia's Tesla, Fermi, Kepler, Maxwell or AMD's TeraScale, GCN, RDNA), the brand (like Nvidia GeForce, Quadro, Tesla or AMD Radeon, Radeon Pro, Radeon Instinct) and the specific model.
Integer Instruction Throughput
- The 32-bit integer performance can be architecture and operation depended less than 32-bit FLOP or 24-bit integer performance.
- In general registers and Vector-ALUs of consumer brand GPUs are 32-bit wide and have to emulate 64-bit integer operations.
- Some architectures offer higher throughput with lower precision. They quadruple the INT8 or octuple the INT4 throughput.
Floating-Point Instruction Throughput
- Consumer GPU performance is measured usually in single-precision (32-bit) floating-point FMA (fused-multiply-add) throughput.
- Consumer GPUs have in general a lower ratio (FP32:FP64) for double-precision (64-bit) floating-point operations throughput than server brand GPUs.
- Some GPGPU architectures offer half-precision (16-bit) floating-point operation throughput with an FP32:FP16 ratio of 1:2.
Nvidia GeForce GTX 580 (Fermi, CC 2.0) - 32-bit integer operations/clock cycle per compute unit 
MAD 16 MUL 16 ADD 32 Bit-shift 16 Bitwise XOR 32
Max theoretic ADD operation throughput: 32 Ops x 16 CUs x 1544 MHz = 790.528 GigaOps/sec
AMD Radeon HD 7970 (GCN 1.0) - 32-bit integer operations/clock cycle per processing element 
MAD 1/4 MUL 1/4 ADD 1 Bit-shift 1 Bitwise XOR 1
Max theoretic ADD operation throughput: 1 Op x 2048 PEs x 925 MHz = 1894.4 GigaOps/sec
MMAC (matrix-multiply-accumulate) units are used in consumer brand GPUs for neural network based upsampling of video game resolutions, in professional brands for upsampling of images and videos, and in server brand GPUs for accelerating convolutional neural networks in general. Convolutions can be implemented as a series of matrix-multiplications via Winograd-transformations . Mobile SoCs usually have an dedicated neural network engine as MMAC unit.
- With Nvidia Volta series TensorCores were introduced. They offer FP16xFP16+FP32, matrix-multiplication-accumulate-units, used to accelerate neural networks. Turing's 2nd gen TensorCores add FP16, INT8, INT4 optimized computation. Amperes's 3rd gen adds support for BF16, TF32, FP64 and sparsity acceleration.Ada Lovelaces's 4th gen adds support for FP8.
AMD Matrix Cores
- AMD released 2020 its server-class CDNA architecture with Matrix Cores which support MFMA (matrix-fused-multiply-add) operations on various data types like INT8, FP16, BF16, FP32. AMD's CDNA 2 architecture adds FP64 optimized throughput for matrix operations. AMD's RDNA 3 architecture features dedicated AI tensor operation accelerators.
Intel XMX Cores
- Intel added XMX, Xe Matrix eXtensions, cores to the Arc Alchemist GPU series.
One reason GPUs are not used as accelerators for chess engines is the host-device latency, aka. kernel-launch-overhead. Nvidia and AMD have not published official numbers, but in practice there is a measurable latency for null-kernels of 5 microseconds  up to 100s of microseconds . One solution to overcome this limitation is to couple tasks to batches to be executed in one run .
GPUs are much more suited than CPUs to implement and train Convolutional Neural Networks (CNN), and were therefore also responsible for the deep learning boom, also affecting game playing programs combining CNN with MCTS, as pioneered by Google DeepMind's AlphaGo and AlphaZero entities in Go, Shogi and Chess using TPUs, and the open source projects Leela Zero headed by Gian-Carlo Pascutto for Go and its Leela Chess Zero adaption.
The market is split into two categories, integrated and discrete GPUs. The first being the most important by quantity, the second by performance. Discrete GPUs are divided as consumer brands for playing 3D games, professional brands for CAD/CGI programs and server brands for big-data and number-crunching workloads. Each brand offering different feature sets in driver, VRAM, or computation abilities.
AMD line of discrete GPUs is branded as Radeon for consumer, Radeon Pro for professional and Radeon Instinct for server.
RDNA3 architecture in Radeon RX 7000 series was announced on November 3, 2022, featuring dedicated AI tensor operation accelerators.
CDNA2 architecture in MI200 HPC-GPU with optimized FP64 throughput (matrix and vector), multi-chip-module design and Infinity Fabric was unveiled in November, 2021.
CDNA architecture in MI100 HPC-GPU with Matrix Cores was unveiled in November, 2020.
RDNA2 cards were unveiled on October 28, 2020.
RDNA cards were unveiled on July 7, 2019.
Vega GCN 5th gen
Vega cards were unveiled on August 14, 2017.
Polaris GCN 4th gen
Polaris cards were first released in 2016.
Southern Islands GCN 1st gen
Southern Island cards introduced the GCN architecture in 2012.
- AMD Radeon HD 7000 on Wikipedia
- Southern Islands Programming Guide
- Southern Islands Instruction Set Architecture
Apple released its M series SoC (system on a chip) with integrated GPU for desktops and notebooks in 2020.
The ARM Mali GPU variants can be found on various systems on chips (SoCs) from different vendors. Since Midgard (2012) with unified-shader-model OpenCL support is offered.
Intel Xe line of GPUs (released since 2020) is divided as Xe-LP (low-power), Xe-HPG (high-performance-gaming), Xe-HP (high-performace) and Xe-HPC (high-performance-computing).
Nvidia line of discrete GPUs is branded as GeForce for consumer, Quadro for professional and Tesla for server.
Ada Lovelace Architecture
The Ada Lovelace microarchitecture was announced on September 20, 2022, featuring 4th-generation Tensor Cores with FP8, FP16, BF16, TF32 and sparsity acceleration.
The Hopper GPU Datacenter microarchitecture was announced on March 22, 2022, featuring Transfomer Engines for large language models.
The Ampere microarchitecture was announced on May 14, 2020 . The Nvidia A100 GPU based on the Ampere architecture delivers a generational leap in accelerated computing in conjunction with CUDA 11 .
Turing cards were first released in 2018. They are the first consumer cores to launch with RTX, for raytracing, features. These are also the first consumer cards to launch with TensorCores used for matrix multiplications to accelerate convolutional neural networks. The Turing GTX line of chips do not offer RTX or TensorCores.
Pascal cards were first released in 2016.
Maxwell cards were first released in 2014.
PowerVR (Imagination Technologies) licenses IP to third parties (most notable Apple) used for system on a chip (SoC) designs. Since Series5 SGX OpenCL support via licensees is available.
Qualcomm offers Adreno GPUs in various types as a component of their Snapdragon SoCs. Since Adreno 300 series OpenCL support is offered.
Vivante licenses IP to third parties for embedded systems, the GC series offers optional OpenCL support.
- Deep Learning
- Graphics Programming
- Monte-Carlo Tree Search
- Parallel Search
- SIMD and SWAR Techniques
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- Will AMD RDNA2 based Radeon RX 6000 series kick butt with Lc0? by Srdja Matovic, CCC, November 01, 2020
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- GPU rumors 2021 by Srdja Matovic, CCC, April 16, 2021
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- kernel launch latency - CUDA / CUDA Programming and Performance - NVIDIA Developer Forums by LukeCuda, June 18, 2018
- Re: Generate EGTB with graphics cards? by Graham Jones, CCC, January 01, 2019
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