My own conclusions are:
- TeraScale has VLIW design.
- GCN has 16 wide SIMD, executing a Wavefront of 64 threads over 4 cycles.
- RDNA has 32 wide SIMD, executing a Wavefront:32 over 1 cycle and Wavefront:64 over two cycles.
Afaik Nvidia did never official mention SIMD in their papers as hardware architecture, with Tesla they only referred to as SIMT.
Nevertheless, my own conclusions are:
- Tesla has 8 wide SIMD, executing a Warp of 32 threads over 4 cycles.
- Fermi has 16 wide SIMD, executing a Warp of 32 threads over 2 cycles.
- Kepler is somehow odd, not sure how the compute units are partitioned.
- Maxwell and Pascal have 32 wide SIMD, executing a Warp of 32 threads over 1 cycle.
- Volta and Turing seem to have 16 wide FPU SIMDs, but my own experiments show 32 wide VALU.
SIMD + Scalar Unit
It seems every SIMD unit has one scalar unit on GPU architectures, executing things like branch-conditions or special functions the SIMD ALUs are not capable of.
embedded CPU controller
It is not documented in the whitepapers, but it seems that every discrete GPU has an embedded CPU controller (e.g. Nvidia Falcon) who (speculation) launches the kernels.
CPW GPU article
A suggestion of mine, keep this GPU article as an generalized overview of GPUs, with incremental updates for different frameworks and architectures. GPUs and GPGPU is a moving target with different platforms offering new feature sets, better open own articles for things like GPGPU, SIMT, CUDA, ROCm, oneAPI, Metal or simply link to Wikipedia containing the newest specs and infos.