From Chessprogramming wiki
Jump to: navigation, search

Home * Hardware * GPU

GPU (Graphics Processing Unit),
a specialized processor initially intended for fast image processing. GPUs may have more raw computing power than general purpose CPUs but need a specialized and parallelized way of programming. Leela Chess Zero has proven that a Best-first Monte-Carlo Tree Search (MCTS) with deep learning methodology will work with GPU architectures.


In the 1970s and 1980s RAM was expensive and Home Computers used custom graphics chips to operate directly on registers/memory without a dedicated frame buffer resp. texture buffer, like TIAin the Atari VCS gaming system, GTIA+ANTIC in the Atari 400/800 series, or Denise+Agnus in the Commodore Amiga series. The 1990s would make 3D graphics and 3D modeling more popular, especially for video games. Cards specifically designed to accelerate 3D math, such as SGI Impact (1995) in 3D graphics-workstations or 3dfx Voodoo (1996) for playing 3D games on PCs, emerged. Some game engines could use instead the SIMD-capabilities of CPUs such as the Intel MMX instruction set or AMD's 3DNow! for real-time rendering. Sony's 3D capable chip GTE used in the PlayStation (1994) and Nvidia's 2D/3D combi chips like NV1 (1995) coined the term GPU for 3D graphics hardware acceleration. With the advent of the unified shader architecture, like in Nvidia Tesla (2006), ATI/AMD TeraScale (2007) or Intel GMA X3000 (2006), GPGPU frameworks like CUDA and OpenCL emerged and gained in popularity.

GPU in Computer Chess

There are in main four ways how to use a GPU for chess:

  • As an accelerator in Lc0: run a neural network for position evaluation on GPU
  • Offload the search in Zeta: run a parallel game tree search with move generation and position evaluation on GPU
  • As a hybrid in perft_gpu: expand the game tree to a certain degree on CPU and offload to GPU to compute the sub-tree
  • Neural network training such as Stockfish NNUE trainer in Pytorch[2] or Lc0 TensorFlow Training

GPU Chess Engines


Early efforts to leverage a GPU for general-purpose computing required reformulating computational problems in terms of graphics primitives via graphics APIs like OpenGL or DirextX, followed by first GPGPU frameworks such as Sh/RapidMind or Brook and finally CUDA and OpenCL.

Khronos OpenCL

OpenCL specified by the Khronos Group is widely adopted across all kind of hardware accelerators from different vendors.


AMD supports language frontends like OpenCL, HIP, C++ AMP and with OpenMP offload directives. It offers with ROCm its own parallel compute platform.


Since macOS 10.14 Mojave a transition from OpenCL to Metal is recommended by Apple.


Intel supports OpenCL with implementations like BEIGNET and NEO for different GPU architectures and the oneAPI platform with DPC++ as frontend language.


CUDA is the parallel computing platform by Nvidia. It supports language frontends like C, C++, Fortran, OpenCL and offload directives via OpenACC and OpenMP.


Hardware Model

A common scheme on GPUs with unified shader architecture is to run multiple threads in SIMT fashion and a multitude of SIMT waves on the same SIMD unit to hide memory latencies. Multiple processing elements (GPU cores) are members of a SIMD unit, multiple SIMD units are coupled to a compute unit, with up to hundreds of compute units present on a discrete GPU. The actual SIMD units may have architecture dependent different numbers of cores (SIMD8, SIMD16, SIMD32), and different computation abilities - floating-point and/or integer with specific bit-width of the FPU/ALU and registers. There is a difference between a vector-processor with variable bit-width and SIMD units with fix bit-width cores. Different architecture white papers from different vendors leave room for speculation about the concrete underlying hardware implementation and the concrete classification as hardware architecture. Scalar units present in the compute unit perform special functions the SIMD units are not capable of and MMAC units (matrix-multiply-accumulate units) are used to speed up neural networks further.

Vendor Terminology
AMD Terminology Nvidia Terminology
Compute Unit Streaming Multiprocessor
Stream Core CUDA Core
Wavefront Warp

Hardware Examples

Nvidia GeForce GTX 580 (Fermi) [3][4]

  • 512 CUDA cores @1.544GHz
  • 16 SMs - Streaming Multiprocessors
  • organized in 2x16 CUDA cores per SM
  • Warp size of 32 threads

AMD Radeon HD 7970 (GCN)[5][6]

  • 2048 Stream cores @0.925GHz
  • 32 Compute Units
  • organized in 4xSIMD16, each SIMT4, per Compute Unit
  • Wavefront size of 64 work-items

Wavefront and Warp

Generalized the definition of the Wavefront and Warp size is the amount of threads executed in SIMT fashion on a GPU with unified shader architecture.

Programming Model

A parallel programming model for GPGPU can be data-parallel, task-parallel, a mixture of both, or with libraries and offload-directives also implicitly-parallel. Single GPU threads (work-items in OpenCL) contain the kernel to be computed and are coupled to a work-group, one or multiple work-groups form the NDRange to be executed on the GPU device. The members of a work-group execute the same kernel, can be usually synchronized and have access to the same scratch-pad memory, with an architecture limit of how many work-items a work-group can hold and how many threads can run in total concurrently on the device.

OpenCL Terminology CUDA Terminology
Kernel Kernel
Compute Unit Streaming Multiprocessor
Processing Element CUDA Core
Work-Item Thread
Work-Group Block
NDRange Grid

Thread Examples

Nvidia GeForce GTX 580 (Fermi, CC2) [7]

  • Warp size: 32
  • Maximum number of threads per block: 1024
  • Maximum number of resident blocks per multiprocessor: 32
  • Maximum number of resident warps per multiprocessor: 64
  • Maximum number of resident threads per multiprocessor: 2048

AMD Radeon HD 7970 (GCN) [8]

  • Wavefront size: 64
  • Maximum number of work-items per work-group: 1024
  • Maximum number of work-groups per compute unit: 40
  • Maximum number of Wavefronts per compute unit: 40
  • Maximum number of work-items per compute unit: 2560

Memory Model

OpenCL offers the following memory model for the programmer:

  • __private - usually registers, accessable only by a single work-item resp. thread.
  • __local - scratch-pad memory shared across work-items of a work-group resp. threads of block.
  • __constant - read-only memory.
  • __global - usually VRAM, accessable by all work-items resp. threads.
OpenCL Terminology CUDA Terminology
Private Memory Registers
Local Memory Shared Memory
Constant Memory Constant Memory
Global Memory Global Memory

Memory Examples

Nvidia GeForce GTX 580 (Fermi) [9]

  • 128 KiB private memory per compute unit
  • 48 KiB (16 KiB) local memory per compute unit (configurable)
  • 64 KiB constant memory
  • 8 KiB constant cache per compute unit
  • 16 KiB (48 KiB) L1 cache per compute unit (configurable)
  • 768 KiB L2 cache in total
  • 1.5 GiB to 3 GiB global memory

AMD Radeon HD 7970 (GCN) [10]

  • 256 KiB private memory per compute unit
  • 64 KiB local memory per compute unit
  • 64 KiB constant memory
  • 16 KiB constant cache per four compute units
  • 16 KiB L1 cache per compute unit
  • 768 KiB L2 cache in total
  • 3 GiB to 6 GiB global memory

Unified Memory

Usually data has to be copied between a CPU host and a discrete GPU device, but different architectures from different vendors with different frameworks on different operating systems may offer a unified and accessible address space between CPU and GPU.

Instruction Throughput

GPUs are used in HPC environments because of their good FLOP/Watt ratio. The instruction throughput in general depends on the architecture (like Nvidia's Tesla, Fermi, Kepler, Maxwell or AMD's TeraScale, GCN, RDNA), the brand (like Nvidia GeForce, Quadro, Tesla or AMD Radeon, Radeon Pro, Radeon Instinct) and the specific model.

Integer Instruction Throughput

  • INT32
The 32-bit integer performance can be architecture and operation depended less than 32-bit FLOP or 24-bit integer performance.
  • INT64
In general registers and Vector-ALUs of consumer brand GPUs are 32-bit wide and have to emulate 64-bit integer operations.
  • INT8
Some architectures offer higher throughput with lower precision. They quadruple the INT8 or octuple the INT4 throughput.

Floating-Point Instruction Throughput

  • FP32
Consumer GPU performance is measured usually in single-precision (32-bit) floating-point FMA (fused-multiply-add) throughput.
  • FP64
Consumer GPUs have in general a lower ratio (FP32:FP64) for double-precision (64-bit) floating-point operations throughput than server brand GPUs.
  • FP16
Some GPGPU architectures offer half-precision (16-bit) floating-point operation throughput with an FP32:FP16 ratio of 1:2.

Throughput Examples

Nvidia GeForce GTX 580 (Fermi, CC 2.0) - 32-bit integer operations/clock cycle per compute unit [11]

   MAD 16
   MUL 16
   ADD 32
   Bit-shift 16
   Bitwise XOR 32

Max theoretic ADD operation throughput: 32 Ops x 16 CUs x 1544 MHz = 790.528 GigaOps/sec

AMD Radeon HD 7970 (GCN 1.0) - 32-bit integer operations/clock cycle per processing element [12]

   MAD 1/4
   MUL 1/4
   ADD 1
   Bit-shift 1
   Bitwise XOR 1

Max theoretic ADD operation throughput: 1 Op x 2048 PEs x 925 MHz = 1894.4 GigaOps/sec


MMAC (matrix-multiply-accumulate) units are used in consumer brand GPUs for neural network based upsampling of video game resolutions, in professional brands for upsampling of images and videos, and in server brand GPUs for accelerating convolutional neural networks in general. Convolutions can be implemented as a series of matrix-multiplications via Winograd-transformations [13]. Mobile SoCs usually have an dedicated neural network engine as MMAC unit.

Nvidia TensorCores

With Nvidia Volta series TensorCores were introduced. They offer FP16xFP16+FP32, matrix-multiplication-accumulate-units, used to accelerate neural networks.[14] Turing's 2nd gen TensorCores add FP16, INT8, INT4 optimized computation.[15] Amperes's 3rd gen adds support for BF16, TF32, FP64 and sparsity acceleration.[16]Ada Lovelaces's 4th gen adds support for FP8.[17]

AMD Matrix Cores

AMD released 2020 its server-class CDNA architecture with Matrix Cores which support MFMA (matrix-fused-multiply-add) operations on various data types like INT8, FP16, BF16, FP32. AMD's CDNA 2 architecture adds FP64 optimized throughput for matrix operations. AMD's RDNA 3 architecture features dedicated AI tensor operation acceleration. AMD's CDNA 3 architecture adds support for FP8 and sparse matrix data (sparsity).

Intel XMX Cores

Intel added XMX, Xe Matrix eXtensions, cores to some of the Intel Xe GPU series, like Arc Alchemist and Intel Data Center GPU Max Series.

Host-Device Latencies

One reason GPUs are not used as accelerators for chess engines is the host-device latency, aka. kernel-launch-overhead. Nvidia and AMD have not published official numbers, but in practice there is a measurable latency for null-kernels of 5 microseconds [18] up to 100s of microseconds [19]. One solution to overcome this limitation is to couple tasks to batches to be executed in one run [20].

Deep Learning

GPUs are much more suited than CPUs to implement and train Convolutional Neural Networks (CNN), and were therefore also responsible for the deep learning boom, also affecting game playing programs combining CNN with MCTS, as pioneered by Google DeepMind's AlphaGo and AlphaZero entities in Go, Shogi and Chess using TPUs, and the open source projects Leela Zero headed by Gian-Carlo Pascutto for Go and its Leela Chess Zero adaption.


The market is split into two categories, integrated and discrete GPUs. The first being the most important by quantity, the second by performance. Discrete GPUs are divided as consumer brands for playing 3D games, professional brands for CAD/CGI programs and server brands for big-data and number-crunching workloads. Each brand offering different feature sets in driver, VRAM, or computation abilities.


AMD line of discrete GPUs is branded as Radeon for consumer, Radeon Pro for professional and Radeon Instinct for server.


CDNA3 HPC architecture was unveiled in December, 2023. With MI300A APU model (CPU+GPU+HBM) and MI300X GPU model, both with multi-chip modules design. Featuring Matrix Cores with support for a broad type of precision, as INT8, FP8, BF16, FP16, TF32, FP32, FP64, as well as sparse matrix data (sparsity). Supported by AMD's ROCm open software stack for AMD Instinct accelerators.

Navi 3x RDNA3

RDNA3 architecture in Radeon RX 7000 series was announced on November 3, 2022, featuring dedicated AI tensor operation acceleration.


CDNA2 architecture in MI200 HPC-GPU with optimized FP64 throughput (matrix and vector), multi-chip-module design and Infinity Fabric was unveiled in November, 2021.


CDNA architecture in MI100 HPC-GPU with Matrix Cores was unveiled in November, 2020.

Navi 2x RDNA2

RDNA2 cards were unveiled on October 28, 2020.


RDNA cards were unveiled on July 7, 2019.

Vega GCN 5th gen

Vega cards were unveiled on August 14, 2017.

Polaris GCN 4th gen

Polaris cards were first released in 2016.

Southern Islands GCN 1st gen

Southern Island cards introduced the GCN architecture in 2012.


M series

Apple released its M series SoC (system on a chip) with integrated GPU for desktops and notebooks in 2020.


The ARM Mali GPU variants can be found on various systems on chips (SoCs) from different vendors. Since Midgard (2012) with unified-shader-model OpenCL support is offered.

Valhall (2019)

Bifrost (2016)

Midgard (2012)



Intel Xe line of GPUs (released since 2020) is divided as Xe-LP (low-power), Xe-HPG (high-performance-gaming), Xe-HP (high-performace) and Xe-HPC (high-performance-computing).


Nvidia line of discrete GPUs is branded as GeForce for consumer, Quadro for professional and Tesla for server.

Grace Hopper Superchip

The Nvidia GH200 Grace Hopper Superchip was unveiled August, 2023 and combines the Nvidia Grace CPU (ARM v9) and Nvidia Hopper GPU architectures via NVLink to deliver a CPU+GPU coherent memory model for accelerated AI and HPC applications.

Ada Lovelace Architecture

The Ada Lovelace microarchitecture was announced on September 20, 2022, featuring 4th-generation Tensor Cores with FP8, FP16, BF16, TF32 and sparsity acceleration.

Hopper Architecture

The Hopper GPU Datacenter microarchitecture was announced on March 22, 2022, featuring Transfomer Engines for large language models.

Ampere Architecture

The Ampere microarchitecture was announced on May 14, 2020 [21]. The Nvidia A100 GPU based on the Ampere architecture delivers a generational leap in accelerated computing in conjunction with CUDA 11 [22].

Turing Architecture

Turing cards were first released in 2018. They are the first consumer cores to launch with RTX, for raytracing, features. These are also the first consumer cards to launch with TensorCores used for matrix multiplications to accelerate convolutional neural networks. The Turing GTX line of chips do not offer RTX or TensorCores.

Volta Architecture

Volta cards were released in 2017. They were the first cards to launch with TensorCores, supporting matrix multiplications to accelerate convolutional neural networks.

Pascal Architecture

Pascal cards were first released in 2016.

Maxwell Architecture

Maxwell cards were first released in 2014.


PowerVR (Imagination Technologies) licenses IP to third parties (most notable Apple) used for system on a chip (SoC) designs. Since Series5 SGX OpenCL support via licensees is available.




Qualcomm offers Adreno GPUs in various types as a component of their Snapdragon SoCs. Since Adreno 300 series OpenCL support is offered.


Vivante Corporation

Vivante licenses IP to third parties for embedded systems, the GC series offers optional OpenCL support.


See also




2008 ...






2015 ...


Chapter 8 in Ross C. Walker, Andreas W. Götz (2016). Electronic Structure Calculations on Graphics Processing Units: From Quantum Chemistry to Condensed Matter Physics. John Wiley & Sons



Forum Posts

2005 ...

2010 ...


Re: Possible Board Presentation and Move Generation for GPUs by Steffan Westcott, CCC, March 20, 2011



2015 ...



Re: How good is the RTX 2080 Ti for Leela? by Ankan Banerjee, CCC, September 16, 2018


2020 ...

External Links




Deep Learning

Game Programming

GitHub - gcp/leela-zero: Go engine with no human-provided knowledge, modeled after the AlphaGo Zero paper

Chess Programming


  1. Image by Mahogny, February 09, 2008, Wikimedia Commons
  2. Pytorch NNUE training by Gary Linscott, CCC, November 08, 2020
  3. Fermi white paper from Nvidia
  4. GeForce 500 series on Wikipedia
  5. Graphics Core Next on Wikipedia
  6. Radeon HD 7000 series on Wikipedia
  7. CUDA Technical_Specification on Wikipedia
  8. AMD GPU Hardware Basics
  9. CUDA C Programming Guide v7.0, Appendix G.COMPUTE CAPABILITIES
  10. AMD Accelerated Parallel Processing OpenCL Programming Guide rev2.7, Appendix D Device Parameters, Table D.1 Parameters for 7xxx Devices
  11. CUDA C Programming Guide v7.0, Chapter 5.4.1. Arithmetic Instructions
  12. AMD_OpenCL_Programming_Optimization_Guide.pdf 3.0beta, Chapter 2.7.1 Instruction Bandwidths
  13. Re: To TPU or not to TPU... by Rémi Coulom, CCC, December 16, 2017
  15. AnandTech - Nvidia Turing Deep Dive page 6
  16. Wikipedia - Ampere microarchitecture
  17. - Ada Lovelace microarchitecture
  18. host-device latencies? by Srdja Matovic, Nvidia CUDA ZONE, Feb 28, 2019
  19. host-device latencies? by Srdja Matovic AMD Developer Community, Feb 28, 2019
  20. Re: GPU ANN, how to deal with host-device latencies? by Milos Stanisavljevic, CCC, May 06, 2018
  21. NVIDIA Ampere Architecture In-Depth | NVIDIA Developer Blog by Ronny Krashinsky, Olivier Giroux, Stephen Jones, Nick Stam and Sridhar Ramaswamy, May 14, 2020
  22. CUDA 11 Features Revealed | NVIDIA Developer Blog by Pramod Ramarao, May 14, 2020
  23. Photon mapping from Wikipedia
  24. Cell (microprocessor) from Wikipedia
  25. Jetson TK1 Embedded Development Kit | NVIDIA
  26. Jetson GPU architecture by Dann Corbit, CCC, October 18, 2016
  27. PowerVR from Wikipedia
  28. Density functional theory from Wikipedia
  29. Yaron Shoham, Sivan Toledo (2002). Parallel Randomized Best-First Minimax Search. Artificial Intelligence, Vol. 137, Nos. 1-2
  30. Alberto Maria Segre, Sean Forman, Giovanni Resta, Andrew Wildenberg (2002). Nagging: A Scalable Fault-Tolerant Paradigm for Distributed Search. Artificial Intelligence, Vol. 140, Nos. 1-2
  31. Tesla K20 GPU Compute Processor Specifications Released | techPowerUp
  32. Parallel Thread Execution from Wikipedia
  33. NVIDIA Compute PTX: Parallel Thread Execution, ISA Version 1.4, March 31, 2009, pdf
  34. ankan-ban/perft_gpu · GitHub
  35. Tensor processing unit from Wikipedia
  36. GeForce 20 series from Wikipedia
  37. Phoronix Test Suite from Wikipedia
  38. kernel launch latency - CUDA / CUDA Programming and Performance - NVIDIA Developer Forums by LukeCuda, June 18, 2018
  39. Re: Generate EGTB with graphics cards? by Graham Jones, CCC, January 01, 2019
  40. Fast perft on GPU (upto 20 Billion nps w/o hashing) by Ankan Banerjee, CCC, June 22, 2013

Up one Level