X86-64

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Home * Hardware * x86-64

Quad-core AMD Opteron processor [1]

x86-64 or x64,
an 64-bit x86-extension, designed by AMD as Hammer- or K8 architecture with Athlon 64 and Opteron cpus. It has been cloned by Intel under the name EMT64 and later Intel 64. Beside 64-bit general purpose extensions, x86-64 supports MMX-, x87- as well as the 128-bit SSE- and SSE2-instruction sets. According to the CPUID-instructions, further SIMD Streamig Extensions, such as SSE3, SSSE3 (Intel only), SSE4 (Core2, K10), AVX, AVX2 and AVX-512, and AMD's 3DNow!, Enhanced 3DNow! and XOP.

Register File

x86-64 doubles the number of x86 general purpose- and XMM registers.

General Purpose

The 16 general purpose registers may be treated as 64 bit Quad Word (bitboard), 32 bit Double Word, 16 bit Word and high, low Byte:

64 32 16 8 high 8 low Purpose
RAX EAX AX AH AL GP, Accumulator
RBX EBX BX BH BL GP, Index Register
RCX ECX CX CH CL GP, Counter, variable shift, rotate via CL
RDX EDX DX DH DL GP, high Accumulator mul/div
RSI ESI SI - - GP, Source Index
RDI EDI DI - - GP, Destination Index
RSP ESP SP - - Stack Pointer
RBP EBP BP - - GP, Base Pointer
R08 R08D R08W R08H R08L GP
.. .. .. .. .. GP
R15 R15D R15W R15H R15L GP

MMX

Eight 64-bit MMX-Registers: MM0 - MM7. Treated as Double, Quad Word or vector of two Floats, Double Words, vector if four Words or eight Bytes.

SSE/SSE*

Sixteen 128-bit XMM-Registers: XMM0 - XMM15. Treated as vector of two Doubles or Quad Words, as vector of four Floats or Double Words, and as vector of eight Words or 16 Bytes.

AVX, AVX2/XOP

Intel Sandy Bridge and AMD Bulldozer Sixteen 256-bit YMM-Registers: YMM0 - YMM15 (shared by XMM as lower half). Treated as vector of four Doubles or Quad Words, as vector of eight Floats or Double Words, and as vector of 15 Words or 32 Bytes.

AVX-512

Intel Xeon Phi (2015) 32 512-bit ZMM-Registers: ZMM0 - ZMM31 Eight vector mask registers

Instructions

Useful instructions for bitboard-applications are by default not supported by high-level programming languages. Available through (inline) Assembly or compiler intrinsics of various C-Compilers [2].

General Purpose

x86-64 Instructions, C-Intrinsic reference from x64 (amd64) Intrinsics List | Microsoft Docs

Mnemonic Description C-Intrinsic Remark
bsf bit scan forward _BitScanForward64
bsr bit scan reverse _BitScanReverse64
bswap byte swap _byteswap_uint64
bt bit test _bittest64
btc bit test and complement _bittestandcomplement64
btr bit test and reset _bittestandreset64
bts bit test and set _bittestandset64
cpuid cpuid _cpuid cpuid
imul signed multiplication _mulh, _mul128
lzcnt leading zero count _lzcnt16, _lzcnt, _lzcnt64 cpuid, SSE4a
mul unsigned multiplication _umulh, _umul128
popcnt population count _popcnt16, _popcnt, _popcnt64 cpuid, SSE4.2, SSE4a
rdtsc read performance counter _rdtsc
rol, ror rotate left, right _rotl, _rotl64, _rotr, _rotr64

Bit-Manipulation

SSE2

{{SSE2 Instructions]]

Software

Operating Systems

Development

Assembly

C-Compiler

See also

General Setwise Operations
BitScan

Publications

Manuals

Agner Fog

AMD

Instructions

Optimization Guides

Intel

Instructions

Optimization Guides

Forum Posts

External Links

AMD

Intel

Instruction Sets

AVX-512 from Wikipedia » AVX-512

Security Vulnerability

References

  1. ↑ Die shot of AMD Opteron quad-core processor, Wikimedia Commons
  2. ↑ Intel(R) C++ Compiler User and Reference Guides covers Intrinsics
  3. ↑ Georg Hager's Blog | Random thoughts on High Performance Computing
  4. ↑ Intel Nehalem Core i3
  5. ↑ Application binary interface from Wikipedia

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