BMI2

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BMI2,
an x86-64 expansion of bit-manipulation instructions by Intel. Like BMI1, BMI2 employs VEX prefix encoding to support three-operand syntax with non-destructive source operands on 32- or 64-bit general-purpose registers. Along with AVX2, BMI2 was expected to be part of Intel's Haswell architecture planned for 2013, but was not yet available in one of the first tested Haswell generations of mid 2013 as reported by Andreas Stiller from the German c't magazine [1]. BMI2 requires bit 8 set in EBX of CPUID with EAX=07H, ECX=0H [2]. In 2017, BMI2 was further incorporated in AMD's Zen-architecture but until Zen 3 in November 2020 [3] with a slow implementation of critical instructions such as PDEP and PEXT [4] [5] [6].

Instructions

Beside the instructions explained in more detail below, there is MULX, Unsigned Multiply, and RORX, SARX/SHLX/SHRX, that is rotate and shifts without affecting processor flags. PEXT and PDEP [7] allow for an alternative of kindergarten- or magic bitboards, and clearly makes maintaining rotated bitboards obsolete [8].

BZHI

Zero High Bits Starting with Specified Bit Position. 

dest ::= src & ((1 << index)-1);

unsigned __int64 _bzhi_u64(unsigned __int64 src, unsigned __int32 index);

PDEP

Parallel Bits Deposit. May be used to map first rank attacks to any rank, file, or diagonal on the chess board.

Intrinsic Prototype

unsigned __int64 pdep_u64(unsigned __int64 src, unsigned __int64 mask);

Sample

SRC1   ┌───┬───┬───┬───┬───┐    ┌───┬───┬───┬───┬───┬───┬───┬───┐
       │S63│S62│S61│S60│S59│....│ S7│ S6│ S5│ S4│ S3│ S2│ S1│ S0│ 
       └───┴───┴───┴───┴───┘    └───┴───┴───┴───┴───┴───┴───┴───┘

SRC2   ┌───┬───┬───┬───┬───┐    ┌───┬───┬───┬───┬───┬───┬───┬───┐
(mask) │ 0 │ 0 │ 0 │ 1 │ 0 │0...│ 1 │ 0 │ 1 │ 0 │ 0 │ 1 │ 0 │ 0 │  (f.i. 4 bits set)
       └───┴───┴───┴───┴───┘    └───┴───┴───┴───┴───┴───┴───┴───┘

DEST   ┌───┬───┬───┬───┬───┐    ┌───┬───┬───┬───┬───┬───┬───┬───┐
       │ 0 │ 0 │ 0 │ S3│ 0 │0...│ S2│ 0 │ S1│ 0 │ 0 │ S0│ 0 │ 0 │ 
       └───┴───┴───┴───┴───┘    └───┴───┴───┴───┴───┴───┴───┴───┘

Serial Implementation

in C [9]: 

U64 _pdep_u64(U64 val, U64 mask) {
  U64 res = 0;
  for (U64 bb = 1; mask; bb += bb) {
    if (val & bb)
      res |= mask & -mask;
    mask &= mask - 1;
  }
  return res;
}

PEXT

Parallel Bits Extract. Great to get the inner six bit occupancy of any rank, file, or diagonal as index of six consecutive lower bit, or the up to 12 bits for a magic attack lookup.

Intrinsic Prototype

unsigned __int64 _pext_u64(unsigned __int64 src, unsigned __int64 mask);

Sample

SRC1   ┌───┬───┬───┬───┬───┐    ┌───┬───┬───┬───┬───┬───┬───┬───┐
       │S63│S62│S61│S60│S59│....│ S7│ S6│ S5│ S4│ S3│ S2│ S1│ S0│ 
       └───┴───┴───┴───┴───┘    └───┴───┴───┴───┴───┴───┴───┴───┘

SRC2   ┌───┬───┬───┬───┬───┐    ┌───┬───┬───┬───┬───┬───┬───┬───┐
(mask) │ 0 │ 0 │ 0 │ 1 │ 0 │0...│ 1 │ 0 │ 1 │ 0 │ 0 │ 1 │ 0 │ 0 │  (f.i. 4 bits set)
       └───┴───┴───┴───┴───┘    └───┴───┴───┴───┴───┴───┴───┴───┘

DEST   ┌───┬───┬───┬───┬───┐    ┌───┬───┬───┬───┬───┬───┬───┬───┐
       │ 0 │ 0 │ 0 │ 0 │ 0 │0...│ 0 │ 0 │ 0 │ 0 │S60│ S7│ S5│ S2│ 
       └───┴───┴───┴───┴───┘    └───┴───┴───┴───┴───┴───┴───┴───┘

Serial Implementation

in C [10], quite similar to PDEP in traversing the mask, and only two expressions, "mask & -mask" and "bb" swapped: 

U64 _pext_u64(U64 val, U64 mask) {
  U64 res = 0;
  for (U64 bb = 1; mask; bb += bb) {
    if ( val & mask & -mask )
      res |= bb;
    mask &= mask - 1;
  }
  return res;
}

Applications

PEXT Bitboards

Fancy PEXT Bitboards as replacement for Fancy Magic Bitboards. The relevant up to four ray occupancies are mapped to a dense index range by using the PEXT instruction: 

U64 arrAttacks  [...]; // ~840 KByte all rook and bishop attacks
U64 arrRookMask  [64]; // 10..12 relevant occupancy bits per rook square
U64 arrBishopMask[64]; //  5.. 9 relevant occupancy bits per bishop square
U32 arrRookBase  [64]; // arrAttacks base offset per rook square
U32 arrBishopBase[64]; // arrAttacks base offset per bishop square

U64 rookAttack(U64 occ, enumSquare sq) {
  return arrAttacks[arrRookBase[sq] + _pext_u64(occ, arrRookMask[sq])];
}

U64 bishopAttack(U64 occ, enumSquare sq) {
  return arrAttacks[arrBishopBase[sq] + _pext_u64(occ, arrBishopMask[sq])];
}

PEXT/PDEP Bitboards

An idea for denser sliding attack tables is also using PDEP, dividing the table size of the PEXT Bitboards by four but some trailing computation. Looking up 16-bit words instead of bitboards - to get the scattered bits of the up to four ray attacks per square in an extracted form mapped to a 16-bit word, which then becomes the attack bitboard by performing a deposit instruction with an appropriate second mask per square. The technique was introduced by Zach Wegner in CCC [11] [12] and implemented by Ronald de Man with a table of slightly more than 210 KiB [13] [14]. Ronald's code was tested by Jean-Francois Romang using Stockfish as testbed, giving promising results [15] [16].

FEN Compression

Concerning the application of neural network training, in particular NNUE training with millions of chess position inside a huge file of FEN records, Lucas Braesch proposed the idea to compress a chess position by a sequence of PEXT instructions, while the decompression is done by an sequence of corresponding PDEP instructions [17]. This is intended as possible alternative of the Huffman coding as applied in the PyTorch NNUE code by Gary Linscott [18]. The table illustrates the layout:

Item Bits Definition
occupancy rocc
(remaining occupancy) 		64 rocc = white | black
pext(white, rocc) cnt(rocc)
black = rocc ^ white 0
pext(pawns, rocc) cnt(rocc)
pext(knights, rocc) cnt(rocc) rocc ^= pawns
pext(bishops, rocc) cnt(rocc) rocc ^= bishops
pext(rooks, rocc) cnt(rocc) rocc ^= rooks
pext(queens, rocc) cnt(rocc) rocc ^= queens
kings = rocc 0
side to move 1
ep 1
pext(epSquare, candis) cnt(candis) candis = ((white & pawns & rank4) << 8)
| ((black & pawns & rank6) >> 8)
pext(castler, rooks) cnt(rooks) castler = rooks with castling rights
(any color)
rule50 7

The uncompressed piece placement bitstream is based on the dense bitboard board-definition and consists of the occupancy, one color bitboard (e.g. White pieces), and subsequently the piece bitboards of both colors, from pawns, knights, bishops, rooks until queens. King bitboards are redundant, due to the subsequent relative complement of a remaining occupancy with all mentioned piece bitboards. Instead of storing the sparsely populated piece bitboards, the compression is due to saving their extracted bits from the remaining occupancy - with bit size of population count of the remaining occupancy, rather than 64. The pseudo code below omits further aspects of a chess position, such as side to move, castling ability, en passant target square and halfmove clock. 

BitStream compress(const U64 * pieceBB, ...) {
  BitStream stream;
  U64 rocc = pieceBB[nWhite] | pieceBB[nBlack];
  stream.write_n_bit(rocc, 64);
  stream.write_n_bit(_pext_u64(pieceBB[nWhite], rocc), popCount(rocc));
  for (pt = nPawn; pt <= nQueen; ++pt) { 
    stream.write_n_bit(_pext_u64(pieceBB[pt], rocc), popCount(rocc));
    rocc ^= pieceBB[pt]; 
  }
  assert (rocc == pieceBB[nKing]);
  // side to move, ep and castling omitted
  return stream;
}

void decompress (const BitStream &stream, U64 * pieceBB, ...) {
  U64 rocc = stream.read_n_bit(64);
  pieceBB[nWhite] = _pdep_u64(stream.read_n_bit(popCount(rocc)), rocc);
  pieceBB[nBlack] = rocc ^ pieceBB[nWhite];
  for (pt = nPawn; pt <= nKing; ++pt) { 
    pieceBB[pt] = _pdep_u64(stream.read_n_bit(popCount(rocc)), rocc);
    rocc ^= pieceBB[pt]; 
  }
  assert (rocc == 0);
  // side to move, ep and castling omitted
}

Syzygy Generator

Ronald de Man's generator for Syzygy Bases can take profit of PDEP and PEXT instructions, or to use their serial implementations to further reduce the size of his already compact endgame tablebases [19].

Early PEXT/PDEP Proposal

In late 2006, Michael Sherwin already proposed a PEXTPDEP instruction, Parallel Bits Extract controlled by a source mask followed by Parallel Bits Deposit controlled by a destination mask [20] [21]. However, it is not known whether his proposal was recognized by Intel engineers and had any influence on the design of the BMI2 PEXT and PDEP instructions.

See also

Forum Posts

2006

2011 ...

2015 ...

Re: Ryzen 2 and BMI2? by Joost Buijs, CCC, May 18, 2020 » AVX2

2020 ...

Re: New AMD Zen 3 and Ryzen processors by Mike Sherwin, CCC, October 11, 2020 » Early PEXT/PDEP Proposal

External Links

References

  1. ↑ Andreas Stiller (2013). Der Rechenkünstler. c't Magazin für Computertechnik 14/2013, p. 114-119 (German)
  2. ↑ How to detect New Instruction support in the 4th generation Intel® Core™ processor family | Intel® Developer Zone by Max Locktyukhin, August 05, 2013
  3. ↑ Zen3 supports fast PEXT aka BMI2 by Alayan Feh, CCC, November 05, 2020
  4. ↑ Ryzen Fritz Chess Benchmarks ? by ralunger, Rybka Forum, March 03, 2017
  5. ↑ Ryzen and BMI2: Strange behavior and high latencies by DonnieTinyHands, Reddit, March 20, 2017 » AMD, BMI2 PEXT
  6. ↑ Re: AMD Announces a Red October: Zen 3 on October 8, RDNA2 on October 28 by dragontamer5788, TechPowerUp Forum, September 9, 2020
  7. ↑ Ruby Lee, Zhijie Shi, Xiao Yang (2001). Efficient Permutation Instructions for Fast Software Cryptography. Micro, IEEE, Vol. 21, No. 6, pdf
  8. ↑ Haswell New Instructions by Zach Wegner, CCC, September 09, 2011
  9. ↑ Re: PEXT Bitboards by Ronald de Man, CCC, June 07, 2013
  10. ↑ Re: PEXT Bitboards by Gerd Isenberg, CCC, June 07, 2013
  11. ↑ Haswell New Instructions by Zach Wegner, CCC, September 09, 2011
  12. ↑ Re: Haswell New Instructions by Gerd Isenberg, CCC, September 12, 2011
  13. ↑ Re: 152k rook and bishop attacks using PEXT and PDEP by Ronald de Man, CCC, October 06, 2013
  14. ↑ tb/src/bmi2.h at master · syzygy1/tb · GitHub by Ronald de Man
  15. ↑ Re: Stockfish haswell optimized build by Jean-Francois Romang, CCC, April 06, 2014
  16. ↑ Stockfish/src/bitboard.h at bmi2 · jromang/Stockfish · GitHub by Jean-Francois Romang
  17. ↑ Re: FEN compression by lucasart, CCC, March 17, 2021 » Forsyth-Edwards Notation, NNUE Training
  18. ↑ nnue-pytorch/nnue_training_data_formats.h at master · glinscott/nnue-pytorch · GitHub
  19. ↑ Re: PEXT Bitboards by Ronald de Man, CCC, June 07, 2013
  20. ↑ New instruction that intel/amd should add by Michael Sherwin, Winboard Forum, December 05, 2006
  21. ↑ Re: New AMD Zen 3 and Ryzen processors by Mike Sherwin, CCC, October 11, 2020

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