Difference between revisions of "ARM2"
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=Computer Chess= | =Computer Chess= | ||
The ARM2 processor was embedded inside the [[TASC]] [[ChessMachine]] plugged in as [https://en.wikipedia.org/wiki/ISA_bus ISA card] inside an [[IBM PC]], running [[Gideon]] and [[The King]] <ref>[https://www.schach-computer.info/wiki/index.php/TASC_ChessMachine TASC ChessMachine] from [https://www.schach-computer.info/wiki/index.php/Hauptseite_En Schachcomputer.info Wiki]</ref>, and was further used in various [[Dedicated Chess Computers|dedicated chess computers]] by [[Hegener & Glaser]] such as the [[Mephisto RISC]]. | The ARM2 processor was embedded inside the [[TASC]] [[ChessMachine]] plugged in as [https://en.wikipedia.org/wiki/ISA_bus ISA card] inside an [[IBM PC]], running [[Gideon]] and [[The King]] <ref>[https://www.schach-computer.info/wiki/index.php/TASC_ChessMachine TASC ChessMachine] from [https://www.schach-computer.info/wiki/index.php/Hauptseite_En Schachcomputer.info Wiki]</ref>, and was further used in various [[Dedicated Chess Computers|dedicated chess computers]] by [[Hegener & Glaser]] such as the [[Mephisto RISC]]. | ||
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=See also= | =See also= | ||
Latest revision as of 21:31, 27 December 2019
ARM2, (ARM3)
the Acorn RISC Machine ARMv2 architecture is a 32-bit CMOS reduced instruction set computer, first released in 1987 [1] as successor of the initial ARM (1985), designed by Sophie Wilson and Steve Furber in 1984. It features a 32-bit data bus, a 26-bit address space and sixteen 32-bit registers (r0 - r15, including PC and SP) [2], and a 3-stage pipelined (Fetch, Decode, Execute) Von Neumann architecture.
The ARM is a bi endian machine, per default little-endian.
Features
The ARM instruction set features three operand instructions, and conditional execution to avoid conditional branches. Some sample ARM assembly [3] :
CMP r0, r1 ; set flags ADDGE r2, r2, r3 ; if (r0 >= r1) then r2 := r2 + r3; ADDLT r2, r2, r4 ; else r2 := r2 + r4;
A 32-bit barrel shifter can be used without performance penalty with most arithmetic instructions and address calculations:
ADD r2, r3, r3, lsl #2 ; r2 := r3 + (r3 << 2)
; → r2 := r3 + r3 * 4
; → r2 := r3 * 5
Computer Chess
The ARM2 processor was embedded inside the TASC ChessMachine plugged in as ISA card inside an IBM PC, running Gideon and The King [4], and was further used in various dedicated chess computers by Hegener & Glaser such as the Mephisto RISC.
See also
Manuals
- ARM® and Thumb®-2 Instruction Set Quick Reference Card (pdf)
- ARM Assembly Language Programming by Pete Cockerell
Postings
- Some facts about the Acorn RISC Machine by Roger Wilson, comp.arch, November 02, 1988
- StrongARM speed of Streater program (was Re: M-Chess Pro 6.0 program description) by Stephen B. Streater, rgcc, October 21, 1996 » reply to Ed Schröder on ARM2 vs. StrongARM
External Links
- Acorn RISC Machine: ARM2 from Wikipedia
- Amber (processor core) from Wikipedia
- ARM2 - Microarchitectures - Acorn - WikiChip
- ARM3 - Microarchitectures - Acorn - WikiChip
- ARMwiki
- ARM Assembler
- Instruction set quick finder
- ARM from Schachcomputer.info Wiki
- RISC OS from Wikipedia
- ARM Hardware Overview
- ARM Information Center
- Race to Embedded World Domination by Paul DeMone, Real World Tech, November 9, 2000
References
- ↑ Some facts about the Acorn RISC Machine by Roger Wilson, comp.arch, November 02, 1988
- ↑ ARM Assembly Language Programming - Chapter 2 - Inside the ARM
- ↑ Samples from ARM-Architektur - Besonderheiten des Befehlssatzes | Wikipedia.de (German)
- ↑ TASC ChessMachine from Schachcomputer.info Wiki
