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AltiVec, (Velocity Engine by Apple and VMX by IBM)
a SIMD instruction set designed by Apple, IBM, and Freescale Semiconductor (formerly Motorola's Semiconductor Products Sector) - the AIM alliance, introduced with Motorola's PowerPC G4, and Apple's PowerPC G5, now owned by NXP Semiconductors and standard part of the Power ISA v.2.03. AltiVec features 32 128-bit vector registers that represent vectors of either 16 bytes, eight 16-bit (half) words or four 32-bit words or floats. Most VMX/AltiVec instructions take three register operands. AltiVec has a flexible vector permute instruction (vperm), which can take arbitrary bytes from two source registers and places them in any position in a destination register controlled by an index register [1]. GCC and other compilers provide intrinsics for AltiVec instructions from C or C++ source code, or include auto-vectorization [2].


AltiVec instructions are very well suited for bitboard fill algorithms and branchless move generation techniques à la DirGolem. Since one 128-bit AltiVec register, keeping up to two bitboards, may treated as vector of 16 bytes, shifting techniques such as one step in all eight directions can be done more efficiently with respect to wraps from a- to the h-file or vice versa. North and south shifts by +-8 of each bitboard can be done with one vperm-instruction simultaniously, while west and east shifts can be done by bytewise shift left/right one.

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