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SSE
,Created page with "'''Home * Hardware * x86 * SSE''' '''SSE''' (Streaming SIMD Extensions), <br/> were introduced by Intel in 1999 in thei..."
'''[[Main Page|Home]] * [[Hardware]] * [[x86]] * SSE'''
'''SSE''' (Streaming [[SIMD and SWAR Techniques|SIMD]] Extensions), <br/>
were introduced by [[Intel]] in 1999 in their [https://en.wikipedia.org/wiki/Pentium_III Pentium III] series of processors. SSE provides an [https://en.wikipedia.org/wiki/Instruction_set instruction set] on eight 128-bit xmm registers xmm0..xmm7, with [[x86-64]] expanded to 16 registers xmm0..xmm15, keeping [[Array|vectors]] of four [[Float|floats]]. Further, as a reply to [[AMD|AMD's]] [https://en.wikipedia.org/wiki/3DNow! 3DNow!], SSE introduced a few integer instructions extending the [[MMX]] instruction set.
=SSE2=
The [[SSE2]] instruction set as major enhancement to SSE, offers a more [https://en.wikipedia.org/wiki/Orthogonal_instruction_set orthogonal set of instructions] with [[Array|vectors]] of four [[Float|floats]] or two [[Double|doubles]], as well as integer vectors of 16 [[Byte|bytes]], eight [[Word|words]], four [[Double Word|double words]] or two [[Quad Word|quad words]].
=See also=
* [[AltiVec]]
* [[AVX]]
* [[AVX2]]
* [[AVX-512]]
* [[MMX]]
* [[SIMD and SWAR Techniques]]
* [[SSE2]]
* [[SSE3]]
* [[SSSE3]]
* [[SSE4]]
* [[SSE5]]
* [[XOP]]
=Forum Posts=
* [https://www.stmintz.com/ccc/index.php?id=405396 planning a SSE-optimized chess engine] by [[Aart Bik]], [[CCC]], January 12, 2005
* [http://www.talkchess.com/forum/viewtopic.php?t=53220 advanced tapered evalutation] by [[Marco Belli]], [[CCC]], August 08, 2014 » [[Tapered Eval]]
=External Links=
* [https://en.wikipedia.org/wiki/Streaming_SIMD_Extensions Streaming SIMD Extensions From Wikipedia]
* [http://msdn.microsoft.com/en-us/library/t467de55.aspx MSDN - Streaming SIMD Extensions (SSE)]
* [http://msdn.microsoft.com/en-us/library/5eawz414.aspx MSDN - Integer Intrinsics Using Streaming SIMD Extensions]
* [http://msdn.microsoft.com/en-us/library/kbyc8fw2.aspx MSDN - Streaming SIMD Extensions Supported by 3DNow!]
* [http://msdn.microsoft.com/en-us/library/cyxt4d09.aspx MSDN - Streaming SIMD Extensions that Support the Cache]
* [http://stackoverflow.com/questions/661338/sse-sse2-and-sse3-for-gnu-c SSE SSE2 and SSE3 for GNU C++ - Stack Overflow]
* [http://software.intel.com/sites/landingpage/IntrinsicsGuide/ Intel Intrinsics Guide]
'''[[x86|Up one Level]]'''
'''SSE''' (Streaming [[SIMD and SWAR Techniques|SIMD]] Extensions), <br/>
were introduced by [[Intel]] in 1999 in their [https://en.wikipedia.org/wiki/Pentium_III Pentium III] series of processors. SSE provides an [https://en.wikipedia.org/wiki/Instruction_set instruction set] on eight 128-bit xmm registers xmm0..xmm7, with [[x86-64]] expanded to 16 registers xmm0..xmm15, keeping [[Array|vectors]] of four [[Float|floats]]. Further, as a reply to [[AMD|AMD's]] [https://en.wikipedia.org/wiki/3DNow! 3DNow!], SSE introduced a few integer instructions extending the [[MMX]] instruction set.
=SSE2=
The [[SSE2]] instruction set as major enhancement to SSE, offers a more [https://en.wikipedia.org/wiki/Orthogonal_instruction_set orthogonal set of instructions] with [[Array|vectors]] of four [[Float|floats]] or two [[Double|doubles]], as well as integer vectors of 16 [[Byte|bytes]], eight [[Word|words]], four [[Double Word|double words]] or two [[Quad Word|quad words]].
=See also=
* [[AltiVec]]
* [[AVX]]
* [[AVX2]]
* [[AVX-512]]
* [[MMX]]
* [[SIMD and SWAR Techniques]]
* [[SSE2]]
* [[SSE3]]
* [[SSSE3]]
* [[SSE4]]
* [[SSE5]]
* [[XOP]]
=Forum Posts=
* [https://www.stmintz.com/ccc/index.php?id=405396 planning a SSE-optimized chess engine] by [[Aart Bik]], [[CCC]], January 12, 2005
* [http://www.talkchess.com/forum/viewtopic.php?t=53220 advanced tapered evalutation] by [[Marco Belli]], [[CCC]], August 08, 2014 » [[Tapered Eval]]
=External Links=
* [https://en.wikipedia.org/wiki/Streaming_SIMD_Extensions Streaming SIMD Extensions From Wikipedia]
* [http://msdn.microsoft.com/en-us/library/t467de55.aspx MSDN - Streaming SIMD Extensions (SSE)]
* [http://msdn.microsoft.com/en-us/library/5eawz414.aspx MSDN - Integer Intrinsics Using Streaming SIMD Extensions]
* [http://msdn.microsoft.com/en-us/library/kbyc8fw2.aspx MSDN - Streaming SIMD Extensions Supported by 3DNow!]
* [http://msdn.microsoft.com/en-us/library/cyxt4d09.aspx MSDN - Streaming SIMD Extensions that Support the Cache]
* [http://stackoverflow.com/questions/661338/sse-sse2-and-sse3-for-gnu-c SSE SSE2 and SSE3 for GNU C++ - Stack Overflow]
* [http://software.intel.com/sites/landingpage/IntrinsicsGuide/ Intel Intrinsics Guide]
'''[[x86|Up one Level]]'''
