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'''[[Main Page|Home]] * [[Hardware]] * DEC Alpha'''
[[FILE:Alpha AXP 21064 diephoto1.jpg|border|right|thumb| [https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 Die] photo of the DEC Alpha 21064 <ref>Die photo of Alpha AXP 21064, by [https://commons.wikimedia.org/wiki/User:Dyl~commonswiki Dyl], April 02, 2007, [https://en.wikipedia.org/wiki/DEC_Alpha DEC Alpha from Wikipedia], [https://en.wikipedia.org/wiki/Alpha_21064 Alpha 21064 from Wikipedia], [https://creativecommons.org/licenses/by-sa/2.0/ CC-BY-SA]</ref> ]]
'''DEC Alpha''',<br/>
a [https://en.wikipedia.org/wiki/64-bit_computing 64-bit] [https://en.wikipedia.org/wiki/Reduced_instruction_set_computer RISC] processor developed by [[Digital Equipment Corporation]] designed to replace their 32-bit [[VAX]] instruction set. The [https://en.wikipedia.org/wiki/Alpha_21064 21064] was the first Alpha processor introduced as DECchip 21064, code named '''EV4''', in February 1992 <ref>[https://groups.google.com/d/msg/comp.arch/QB59ace2V8M/pEuccRNGoe8J Alpha Architecture Technical Summary] by [https://en.wikipedia.org/wiki/Jim_Gettys Jim Gettys], [https://groups.google.com/forum/#!forum/comp.arch comp.arch], February 25, 1992</ref>, released since September 1992. While Alpha processors were widely used through the 90s in [https://en.wikipedia.org/wiki/Workstation Workstations] and [https://en.wikipedia.org/wiki/Server_%28computing%29 Server], such as [https://en.wikipedia.org/wiki/DEC_3000_AXP DEC 3000 AXP], [https://en.wikipedia.org/wiki/AlphaStation AlphaStation] and [https://en.wikipedia.org/wiki/AlphaServer AlphaServer], running [https://en.wikipedia.org/wiki/OpenVMS OpenVMS], [[Unix#Digital|Digital UNIX]] and even [[Windows|Windows NT]], [https://en.wikipedia.org/wiki/Cray#Cray_Research_Inc._and_Cray_Computer_Corporation:_1972_to_1996 Cray Research] used the 150 MHz Alpha 21064 in their [[Cray T3D]] supercomputer.
The Alpha architecture was sold, along with most parts of DEC, to [https://en.wikipedia.org/wiki/Compaq Compaq] in 1998. Compaq, already an [[Intel]] customer, decided to phase out Alpha in favor of the forthcoming [[Itanium]] architecture, and sold all Alpha intellectual property to Intel in 2001 <ref>[https://en.wikipedia.org/wiki/DEC_Alpha DEC Alpha from Wikipedia]</ref>.
=Architecture=
The Alpha 21064 is a [https://en.wikipedia.org/wiki/Instruction_pipeline superpipelined] dual-issue [https://en.wikipedia.org/wiki/Superscalar superscalar] microprocessor that executes instructions in-order. It is capable of issuing up to two instructions every clock cycle to four functional units: an integer unit, a floating-point unit (FPU), an address unit, and a branch unit. The integer pipeline is seven stages long, and the floating-point pipeline ten stages. The first four stages of both pipelines are identical and are implemented by the [https://en.wikipedia.org/wiki/Alpha_21064#I-box I-Box]. The 21064 implemented a 43-bit [https://en.wikipedia.org/wiki/Virtual_address_space virtual address] and a 34-bit [https://en.wikipedia.org/wiki/Physical_address physical address], and is therefore capable of addressing 8 TiB of [[Memory#Virtual|virtual memory]] and 16 GiB of physical memory.
==Data Types==
In the Alpha [[Little-endian|little-endian]] <ref>[https://wiki.gentoo.org/wiki/Alpha/FAQ#Is_Alpha_big_endian_or_little_endian.3F Alpha/FAQ - Is Alpha big endian or little endian?]</ref> architecture, a [[Byte|byte]] is defined as [https://en.wikipedia.org/wiki/Octet_%28computing%29 octet], a [[Word|word]] as a 16-bit datum, a [[Double Word|longword]] as a 32-bit datum, a [[Quad Word|quadword]] as a 64-bit datum, and an octaword as a 128-bit datum. Floating-point types are either 32-bit [[Float|floats]] or 64-bit [[Double|doubles]], [https://en.wikipedia.org/wiki/IEEE_754-1985 IEEE 754] as well as VAX floating point format for backward compatibility.
==Register File==
The Alpha [https://en.wikipedia.org/wiki/Instruction_set instruction set architecture] (ISA) defined a set of 32 64-bit integer [https://en.wikipedia.org/wiki/Processor_register registers] R0 .. R31, and 32 64-bit floating point registers F0 .. F31, where R31 and F31 were not writable and handwired to zero. The 64-bit [https://en.wikipedia.org/wiki/Program_counter program counter] is longword aligned and incremented by four to the address of the next instruction when an instruction is decoded. A lock flag and locked physical address register are used by the load-locked and store-conditional instructions for multiprocessor support.
==Integer Instructions==
The integer arithmetic instructions perform [https://en.wikipedia.org/wiki/Addition addition], [https://en.wikipedia.org/wiki/Multiplication multiplication], and [https://en.wikipedia.org/wiki/Subtraction subtraction] on longwords or quadwords, [https://en.wikipedia.org/wiki/Relational_operator comparison] on quadwords, and conditional move instructions. Signed and unsigned compare instructions compare two registers or a register and a literal and write '1' to the destination register if the specified condition is true or '0' otherwise. [https://en.wikipedia.org/wiki/Bitwise_operation Bitwise logical] instructions perform [[Combinatorial Logic#AND|AND]] (Logical Product), [[Combinatorial Logic#OR|OR]] (Logical Sum, BIS), and [[Combinatorial Logic#XOR|XOR]] (Logical Difference), while the instructions with the mnemonics BIC, ORNOT and EQV use the complement of the second source operand. [https://en.wikipedia.org/wiki/Bitwise_operation#Bit_shifts Shift instructions] perform [https://en.wikipedia.org/wiki/Arithmetic_shift arithmetic right shift], and [https://en.wikipedia.org/wiki/Logical_shift logical shift] in both directions.
==Count Extensions==
The Count Extensions (CIX) was an integer extension of three instructions for [[Population Count|population count]] and [[BitScan|bitscan]] purposes, first implemented on the [https://en.wikipedia.org/wiki/Alpha_21264#Alpha_21264A Alpha 21264A (EV67)] in late 1999.
{| class="wikitable"
|-
! Mnemonic
! Instruction
|-
| CTLZ
| [[BitScan#LeadingZeroCount|Count Leading Zero]]
|-
| CTPOP
| [[Population Count|Count Population]]
|-
| CTTZ
| [[BitScan#TrailingZeroCount|Count Trailing Zero]]
|}
=21164=
[[FILE:Alpha EV5 die.JPG|border|right|thumb| Die shot of DEC Alpha 21164 <ref>English: Die shot of DEC Alpha 21164 (EV5) microprocessor, by [https://commons.wikimedia.org/wiki/User:Birdman86 Pauli Rautakorpi], 28 June 2013, [https://en.wikipedia.org/wiki/Alpha_21164 Alpha 21164 from Wikipedia], [https://creativecommons.org/licenses/by/3.0 CC BY 3.0]</ref> ]]
The [https://en.wikipedia.org/wiki/Alpha_21164 Alpha 21164] (EV5) was introduced in January 1995. It is a four-issue [https://en.wikipedia.org/wiki/Superscalar superscalar] processor capable of issuing a maximum of four instructions per clock cycle to two integer and two floating-point execution units. The integer [https://en.wikipedia.org/wiki/Instruction_pipeline pipeline] is seven stages long, and the floating-point pipeline is ten stages long. The 21164 implemented a 43-bit virtual address and a 40-bit physical address. The two integer pipelines, add and multiply, are both capable of executing add, logical, load, compare, and conditional move instructions. The multiply pipeline exclusively executes shift, store, and multiply instructions. The add pipeline exclusively executes branch instructions. The 21164 has three levels of cache, two on-die and one external and optional. The primary cache is split into separate caches for instructions and data, referred to as the I-cache and D-cache respectively. They are 8 KB in size, direct-mapped and have a cache line size of 32 bytes. [https://en.wikipedia.org/wiki/Cray#Cray_Research_Inc._and_Cray_Computer_Corporation:_1972_to_1996 Cray Research] used the 300 MHz Alpha 21164 in their [[Cray T3E]] supercomputer.
=21264=
The [https://en.wikipedia.org/wiki/Alpha_21264 Alpha 21264] (EV6), introduced in October 1996, is a four-issue [https://en.wikipedia.org/wiki/Superscalar superscalar] processor with [https://en.wikipedia.org/wiki/Out-of-order_execution out-of-order execution], [https://en.wikipedia.org/wiki/Speculative_execution speculative execution] and a seven-stage [https://en.wikipedia.org/wiki/Instruction_pipeline instruction pipeline]. It has a peak execution rate of six [https://en.wikipedia.org/wiki/Instructions_per_cycle instructions per cycle]. The Alpha 21264 has two levels of cache, a primary cache and secondary cache. The three-level cache of the Alpha 21164 was not used due to problems with bandwidth <ref>[https://en.wikipedia.org/wiki/Alpha_21264#Cache Alpha 21264 - Cache - Wikipedia]</ref>.
=Chess Programs=
at times running on DEC Alpha
* [[Chess Guru]]
* [[Crafty]]
* [[DarkThought]]
* [[Ferret]]
* [[Frenchess]] ([[Cray T3D]])
* [[Shredder]]
* [[The King]]
* [[Zugzwang (Program)|Zugzwang]] ([[Cray T3E]])
=See also=
* [[Cray T3D]]
* [[Cray T3E]]
* [[VAX]]
=Manuals=
* [http://www2.phys.canterbury.ac.nz/dept/docs/manuals/unix/DEC_4.0e_Docs/HTML/PROG_LIB.HTM DIGITAL UNIX Documentation - Programming Guides]
* [http://download.majix.org/dec/alpha_arch_ref.pdf Alpha Architecture Reference Manual] (pdf) [https://en.wikipedia.org/wiki/Compaq Compaq]
* [http://www.cs.cmu.edu/afs/cs/academic/class/15213-f98/doc/alpha-asm.pdf Digital UNIX Assembly Language Programmer's Guide], March 1996 (pdf)
=Publications=
* [http://dblp.uni-trier.de/pers/hd/s/Sites:Richard_L= Richard L. Sites] ('''1992'''). ''Alpha AXP Architecture''. [http://dblp.uni-trier.de/db/journals/dtj/dtj4.html Digital Technical Journal, Vol. 4], No. 4, [http://www.hpl.hp.com/hpjournal/dtj/vol4num4/vol4num4art1.pdf pdf]
=Forum Posts=
* [https://groups.google.com/d/msg/comp.arch/QB59ace2V8M/pEuccRNGoe8J Alpha Architecture Technical Summary] by [https://en.wikipedia.org/wiki/Jim_Gettys Jim Gettys], [https://groups.google.com/forum/#!forum/comp.arch comp.arch], February 25, 1992
* [https://groups.google.com/d/msg/rec.games.chess.computer/d3sYjfVJI7E/0At3bwtgYxgJ Crafty on 767Mhz Alpha at Paris WMCCC?] by Richard A. Fowell, [[Computer Chess Forums|rgcc]], September 27, 1997
=External Links=
* [https://en.wikipedia.org/wiki/DEC_Alpha DEC Alpha from Wikipedia]
* [https://www.cs.arizona.edu/projects/alto/Doc/local/alpha.instruction.html Alpha Instruction Set (Brief)]
* [https://www.cs.tufts.edu/~nr/toolkit/specs/alpha.html Alpha instruction-set specification]
* [http://alasir.com/articles/alpha_history/index.html Alpha: The History in Facts and Comments] by [http://alasir.com/articles/ Paul V. Bolotoff], April 2005
* [https://wiki.gentoo.org/wiki/Alpha/FAQ Alpha/FAQ - Gentoo Wiki] <ref>[https://en.wikipedia.org/wiki/Gentoo_Linux Gentoo Linux from Wikipedia]</ref>
==Processors==
* [https://en.wikipedia.org/wiki/Alpha_21064 Alpha 21064 from Wikipedia]
* [https://en.wikipedia.org/wiki/Alpha_21164 Alpha 21164 from Wikipedia]
* [https://en.wikipedia.org/wiki/Alpha_21264 Alpha 21264 from Wikipedia]
* [https://en.wikipedia.org/wiki/Alpha_21364 Alpha 21364 from Wikipedia]
==Workstations==
* <span id="3000"></span>[https://en.wikipedia.org/wiki/DEC_3000_AXP DEC 3000 AXP from Wikipedia]
* [https://en.wikipedia.org/wiki/DECpc_AXP_150 DECpc AXP 150 from Wikipedia]
* [https://en.wikipedia.org/wiki/AlphaStation AlphaStation from Wikipedia]
==Server==
* [https://en.wikipedia.org/wiki/DEC_4000_AXP DEC 4000 AXP from Wikipedia]
* [https://en.wikipedia.org/wiki/AlphaServer AlphaServer from Wikipedia]
=References=
<references />
'''[[Hardware|Up one Level]]'''
[[Category:Die]]
[[FILE:Alpha AXP 21064 diephoto1.jpg|border|right|thumb| [https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 Die] photo of the DEC Alpha 21064 <ref>Die photo of Alpha AXP 21064, by [https://commons.wikimedia.org/wiki/User:Dyl~commonswiki Dyl], April 02, 2007, [https://en.wikipedia.org/wiki/DEC_Alpha DEC Alpha from Wikipedia], [https://en.wikipedia.org/wiki/Alpha_21064 Alpha 21064 from Wikipedia], [https://creativecommons.org/licenses/by-sa/2.0/ CC-BY-SA]</ref> ]]
'''DEC Alpha''',<br/>
a [https://en.wikipedia.org/wiki/64-bit_computing 64-bit] [https://en.wikipedia.org/wiki/Reduced_instruction_set_computer RISC] processor developed by [[Digital Equipment Corporation]] designed to replace their 32-bit [[VAX]] instruction set. The [https://en.wikipedia.org/wiki/Alpha_21064 21064] was the first Alpha processor introduced as DECchip 21064, code named '''EV4''', in February 1992 <ref>[https://groups.google.com/d/msg/comp.arch/QB59ace2V8M/pEuccRNGoe8J Alpha Architecture Technical Summary] by [https://en.wikipedia.org/wiki/Jim_Gettys Jim Gettys], [https://groups.google.com/forum/#!forum/comp.arch comp.arch], February 25, 1992</ref>, released since September 1992. While Alpha processors were widely used through the 90s in [https://en.wikipedia.org/wiki/Workstation Workstations] and [https://en.wikipedia.org/wiki/Server_%28computing%29 Server], such as [https://en.wikipedia.org/wiki/DEC_3000_AXP DEC 3000 AXP], [https://en.wikipedia.org/wiki/AlphaStation AlphaStation] and [https://en.wikipedia.org/wiki/AlphaServer AlphaServer], running [https://en.wikipedia.org/wiki/OpenVMS OpenVMS], [[Unix#Digital|Digital UNIX]] and even [[Windows|Windows NT]], [https://en.wikipedia.org/wiki/Cray#Cray_Research_Inc._and_Cray_Computer_Corporation:_1972_to_1996 Cray Research] used the 150 MHz Alpha 21064 in their [[Cray T3D]] supercomputer.
The Alpha architecture was sold, along with most parts of DEC, to [https://en.wikipedia.org/wiki/Compaq Compaq] in 1998. Compaq, already an [[Intel]] customer, decided to phase out Alpha in favor of the forthcoming [[Itanium]] architecture, and sold all Alpha intellectual property to Intel in 2001 <ref>[https://en.wikipedia.org/wiki/DEC_Alpha DEC Alpha from Wikipedia]</ref>.
=Architecture=
The Alpha 21064 is a [https://en.wikipedia.org/wiki/Instruction_pipeline superpipelined] dual-issue [https://en.wikipedia.org/wiki/Superscalar superscalar] microprocessor that executes instructions in-order. It is capable of issuing up to two instructions every clock cycle to four functional units: an integer unit, a floating-point unit (FPU), an address unit, and a branch unit. The integer pipeline is seven stages long, and the floating-point pipeline ten stages. The first four stages of both pipelines are identical and are implemented by the [https://en.wikipedia.org/wiki/Alpha_21064#I-box I-Box]. The 21064 implemented a 43-bit [https://en.wikipedia.org/wiki/Virtual_address_space virtual address] and a 34-bit [https://en.wikipedia.org/wiki/Physical_address physical address], and is therefore capable of addressing 8 TiB of [[Memory#Virtual|virtual memory]] and 16 GiB of physical memory.
==Data Types==
In the Alpha [[Little-endian|little-endian]] <ref>[https://wiki.gentoo.org/wiki/Alpha/FAQ#Is_Alpha_big_endian_or_little_endian.3F Alpha/FAQ - Is Alpha big endian or little endian?]</ref> architecture, a [[Byte|byte]] is defined as [https://en.wikipedia.org/wiki/Octet_%28computing%29 octet], a [[Word|word]] as a 16-bit datum, a [[Double Word|longword]] as a 32-bit datum, a [[Quad Word|quadword]] as a 64-bit datum, and an octaword as a 128-bit datum. Floating-point types are either 32-bit [[Float|floats]] or 64-bit [[Double|doubles]], [https://en.wikipedia.org/wiki/IEEE_754-1985 IEEE 754] as well as VAX floating point format for backward compatibility.
==Register File==
The Alpha [https://en.wikipedia.org/wiki/Instruction_set instruction set architecture] (ISA) defined a set of 32 64-bit integer [https://en.wikipedia.org/wiki/Processor_register registers] R0 .. R31, and 32 64-bit floating point registers F0 .. F31, where R31 and F31 were not writable and handwired to zero. The 64-bit [https://en.wikipedia.org/wiki/Program_counter program counter] is longword aligned and incremented by four to the address of the next instruction when an instruction is decoded. A lock flag and locked physical address register are used by the load-locked and store-conditional instructions for multiprocessor support.
==Integer Instructions==
The integer arithmetic instructions perform [https://en.wikipedia.org/wiki/Addition addition], [https://en.wikipedia.org/wiki/Multiplication multiplication], and [https://en.wikipedia.org/wiki/Subtraction subtraction] on longwords or quadwords, [https://en.wikipedia.org/wiki/Relational_operator comparison] on quadwords, and conditional move instructions. Signed and unsigned compare instructions compare two registers or a register and a literal and write '1' to the destination register if the specified condition is true or '0' otherwise. [https://en.wikipedia.org/wiki/Bitwise_operation Bitwise logical] instructions perform [[Combinatorial Logic#AND|AND]] (Logical Product), [[Combinatorial Logic#OR|OR]] (Logical Sum, BIS), and [[Combinatorial Logic#XOR|XOR]] (Logical Difference), while the instructions with the mnemonics BIC, ORNOT and EQV use the complement of the second source operand. [https://en.wikipedia.org/wiki/Bitwise_operation#Bit_shifts Shift instructions] perform [https://en.wikipedia.org/wiki/Arithmetic_shift arithmetic right shift], and [https://en.wikipedia.org/wiki/Logical_shift logical shift] in both directions.
==Count Extensions==
The Count Extensions (CIX) was an integer extension of three instructions for [[Population Count|population count]] and [[BitScan|bitscan]] purposes, first implemented on the [https://en.wikipedia.org/wiki/Alpha_21264#Alpha_21264A Alpha 21264A (EV67)] in late 1999.
{| class="wikitable"
|-
! Mnemonic
! Instruction
|-
| CTLZ
| [[BitScan#LeadingZeroCount|Count Leading Zero]]
|-
| CTPOP
| [[Population Count|Count Population]]
|-
| CTTZ
| [[BitScan#TrailingZeroCount|Count Trailing Zero]]
|}
=21164=
[[FILE:Alpha EV5 die.JPG|border|right|thumb| Die shot of DEC Alpha 21164 <ref>English: Die shot of DEC Alpha 21164 (EV5) microprocessor, by [https://commons.wikimedia.org/wiki/User:Birdman86 Pauli Rautakorpi], 28 June 2013, [https://en.wikipedia.org/wiki/Alpha_21164 Alpha 21164 from Wikipedia], [https://creativecommons.org/licenses/by/3.0 CC BY 3.0]</ref> ]]
The [https://en.wikipedia.org/wiki/Alpha_21164 Alpha 21164] (EV5) was introduced in January 1995. It is a four-issue [https://en.wikipedia.org/wiki/Superscalar superscalar] processor capable of issuing a maximum of four instructions per clock cycle to two integer and two floating-point execution units. The integer [https://en.wikipedia.org/wiki/Instruction_pipeline pipeline] is seven stages long, and the floating-point pipeline is ten stages long. The 21164 implemented a 43-bit virtual address and a 40-bit physical address. The two integer pipelines, add and multiply, are both capable of executing add, logical, load, compare, and conditional move instructions. The multiply pipeline exclusively executes shift, store, and multiply instructions. The add pipeline exclusively executes branch instructions. The 21164 has three levels of cache, two on-die and one external and optional. The primary cache is split into separate caches for instructions and data, referred to as the I-cache and D-cache respectively. They are 8 KB in size, direct-mapped and have a cache line size of 32 bytes. [https://en.wikipedia.org/wiki/Cray#Cray_Research_Inc._and_Cray_Computer_Corporation:_1972_to_1996 Cray Research] used the 300 MHz Alpha 21164 in their [[Cray T3E]] supercomputer.
=21264=
The [https://en.wikipedia.org/wiki/Alpha_21264 Alpha 21264] (EV6), introduced in October 1996, is a four-issue [https://en.wikipedia.org/wiki/Superscalar superscalar] processor with [https://en.wikipedia.org/wiki/Out-of-order_execution out-of-order execution], [https://en.wikipedia.org/wiki/Speculative_execution speculative execution] and a seven-stage [https://en.wikipedia.org/wiki/Instruction_pipeline instruction pipeline]. It has a peak execution rate of six [https://en.wikipedia.org/wiki/Instructions_per_cycle instructions per cycle]. The Alpha 21264 has two levels of cache, a primary cache and secondary cache. The three-level cache of the Alpha 21164 was not used due to problems with bandwidth <ref>[https://en.wikipedia.org/wiki/Alpha_21264#Cache Alpha 21264 - Cache - Wikipedia]</ref>.
=Chess Programs=
at times running on DEC Alpha
* [[Chess Guru]]
* [[Crafty]]
* [[DarkThought]]
* [[Ferret]]
* [[Frenchess]] ([[Cray T3D]])
* [[Shredder]]
* [[The King]]
* [[Zugzwang (Program)|Zugzwang]] ([[Cray T3E]])
=See also=
* [[Cray T3D]]
* [[Cray T3E]]
* [[VAX]]
=Manuals=
* [http://www2.phys.canterbury.ac.nz/dept/docs/manuals/unix/DEC_4.0e_Docs/HTML/PROG_LIB.HTM DIGITAL UNIX Documentation - Programming Guides]
* [http://download.majix.org/dec/alpha_arch_ref.pdf Alpha Architecture Reference Manual] (pdf) [https://en.wikipedia.org/wiki/Compaq Compaq]
* [http://www.cs.cmu.edu/afs/cs/academic/class/15213-f98/doc/alpha-asm.pdf Digital UNIX Assembly Language Programmer's Guide], March 1996 (pdf)
=Publications=
* [http://dblp.uni-trier.de/pers/hd/s/Sites:Richard_L= Richard L. Sites] ('''1992'''). ''Alpha AXP Architecture''. [http://dblp.uni-trier.de/db/journals/dtj/dtj4.html Digital Technical Journal, Vol. 4], No. 4, [http://www.hpl.hp.com/hpjournal/dtj/vol4num4/vol4num4art1.pdf pdf]
=Forum Posts=
* [https://groups.google.com/d/msg/comp.arch/QB59ace2V8M/pEuccRNGoe8J Alpha Architecture Technical Summary] by [https://en.wikipedia.org/wiki/Jim_Gettys Jim Gettys], [https://groups.google.com/forum/#!forum/comp.arch comp.arch], February 25, 1992
* [https://groups.google.com/d/msg/rec.games.chess.computer/d3sYjfVJI7E/0At3bwtgYxgJ Crafty on 767Mhz Alpha at Paris WMCCC?] by Richard A. Fowell, [[Computer Chess Forums|rgcc]], September 27, 1997
=External Links=
* [https://en.wikipedia.org/wiki/DEC_Alpha DEC Alpha from Wikipedia]
* [https://www.cs.arizona.edu/projects/alto/Doc/local/alpha.instruction.html Alpha Instruction Set (Brief)]
* [https://www.cs.tufts.edu/~nr/toolkit/specs/alpha.html Alpha instruction-set specification]
* [http://alasir.com/articles/alpha_history/index.html Alpha: The History in Facts and Comments] by [http://alasir.com/articles/ Paul V. Bolotoff], April 2005
* [https://wiki.gentoo.org/wiki/Alpha/FAQ Alpha/FAQ - Gentoo Wiki] <ref>[https://en.wikipedia.org/wiki/Gentoo_Linux Gentoo Linux from Wikipedia]</ref>
==Processors==
* [https://en.wikipedia.org/wiki/Alpha_21064 Alpha 21064 from Wikipedia]
* [https://en.wikipedia.org/wiki/Alpha_21164 Alpha 21164 from Wikipedia]
* [https://en.wikipedia.org/wiki/Alpha_21264 Alpha 21264 from Wikipedia]
* [https://en.wikipedia.org/wiki/Alpha_21364 Alpha 21364 from Wikipedia]
==Workstations==
* <span id="3000"></span>[https://en.wikipedia.org/wiki/DEC_3000_AXP DEC 3000 AXP from Wikipedia]
* [https://en.wikipedia.org/wiki/DECpc_AXP_150 DECpc AXP 150 from Wikipedia]
* [https://en.wikipedia.org/wiki/AlphaStation AlphaStation from Wikipedia]
==Server==
* [https://en.wikipedia.org/wiki/DEC_4000_AXP DEC 4000 AXP from Wikipedia]
* [https://en.wikipedia.org/wiki/AlphaServer AlphaServer from Wikipedia]
=References=
<references />
'''[[Hardware|Up one Level]]'''
[[Category:Die]]
