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'''[[Main Page|Home]] * [[Hardware]] * Berkeley Chess Microprocessor'''
[[FILE:CampanileMtTamalpiasSunset-original.jpg|220px|border|right|thumb| [https://en.wikipedia.org/wiki/Sather_Tower The Campanile], UC Berkeley <ref>[https://en.wikipedia.org/wiki/Sather_Tower The Campanile] and [https://en.wikipedia.org/wiki/Mount_Tamalpais Mt. Tamalpais] from [https://en.wikipedia.org/wiki/California_Memorial_Stadium Memorial Stadium] at sunset, 2006 by Tristan Harward, [https://en.wikipedia.org/wiki/University_of_California,_Berkeley University of California, Berkeley - Wikipedia]</ref>
]]
'''Berkeley Chess Microprocessor''', (BCM)<br/>
a chess microprocessor developed by [[James Testa]] and [[Alvin M. Despain]] at [[University of California, Berkeley]] <ref>[[James Testa]], [[Alvin M. Despain]] ('''1990'''). ''[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=124744&contentType=Conference+Publications&searchWithin%3Dp_Authors%3A.QT.Testa%2C+J..QT. A CMOS VLSI chess microprocessor]''. [[University of California, Berkeley]], [[IEEE]] Custom Integrated Circuit Conference</ref> , introduced in May 1990 at the ''Custom Integrated Circuits Conference'' <ref>[http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=140 Custom Integrated Circuits Conference, 1990, Proceedings of the IEEE 1990]</ref>, also mentioned in [[Marc Boulé|Marc Boulé's]] 2002 thesis <ref>[[Marc Boulé]] ('''2002'''). ''An FPGA Move Generator for the Game of Chess''. Masters thesis, [[McGill University]], (Supervisor: [[Zeljko Zilic]], Co-Supervisor: [[Monroe Newborn|Monty Newborn]]), [http://www.iml.ece.mcgill.ca/%7Emboule/files/mbthesis02.pdf pdf]</ref>.
The BCM was a 200,000 [https://en.wikipedia.org/wiki/Transistor transistor] [[VLSI Design|VLSI chip]], 1.2 [https://en.wikipedia.org/wiki/Micrometre micron] [https://en.wikipedia.org/wiki/CMOS CMOS] [https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 die], 11 mm by 9 mm in area, able to [[Move Generation|generate]] three million [[Legal Move|legal moves]] per second. The chip incorporates a move generator, a basic [[Evaluation|positional evaluator]] and [[Search|search]] control, can detect [[Pin|pins]] and [[X-ray Attacks (Bitboards)|X-ray attacks]], and has an [[Combinatorial Logic#ALU|ALU]] for each [[Squares|square]] to sum the values of attacking pieces to perform a kind of parallel [[Static Exchange Evaluation|SEE]] for [[Move Ordering|move ordering]] and [[Evaluation|evaluation]] purposes such as [[Mobility|mobility]] and [[Square Control|square control]].
=Move Generation=
While the [[Move Generation|move generation]] design is similar to [[Belle|Belle's]], legal move generation in hardware was already designed by Alvin Despain in the 70s, as described by [[Ozalp Babaoglu]] in his 1977 thesis <ref>[[Ozalp Babaoglu]] ('''1977'''). ''Hardware implementation of the legal move generation and relative ordering functions for the game of chess''. Master's thesis, [[University of California, Berkeley]]</ref> , but as noted by [[Joe Condon]] and [[Ken Thompson]], never obtained funding for full construction <ref>[[Joe Condon]], [[Ken Thompson]] ('''1982'''). ''Belle Chess Hardware''. [[Advances in Computer Chess 3]], Reprinted ('''1988''') in [[Computer Chess Compendium]]</ref> . Both, attackers and victims, emit signals in all directions simultaneously so that it is a matter of [[Combinatorial Logic|combinatorial logic]] in the square receivers to detect pins. [[Belle#FindVictim|Find victim]] and [[Belle#FindAggressor|find attacker]] cycles use programmable priority arbiters for [[Move Ordering|move ordering]] during full width as well as [[Quiescence Search|quiescence search]]. A 25–level ply [[Stack|stack]] to enable or disable [[Origin Square|origin-]] and [[Target Square|target squares]] keeps track of the move generation stage, and controls which move is generated next. This is how the bookkeeping works in sequential [[C]] like pseudo code with [[Bitboards]] (omitting legal move logic):
<pre>
disable[ply] = depth <= 0 ? emptySquares : 0; /* enable to-squares */
while ( ( to = findMVV(disable[ply])) >= 0 ) {
disable[ply] &= ~ownPieces; /* enable all possible from-squares */
while ( ( from = findLVA(disable[ply])) >= 0 ) {
make(from, to); /* ply++ */
....
unmake(from, to); /* ply-- */
disable[ply] |= 1 << from; /* disable from-square */
}
disable[ply] |= 1 << to; /* disable to-square */
}
</pre>
=Zerker=
The Berkeley Chess Microprocessor lacked participation in computer chess competitions. A chess entity of BCM's co-author [[James Testa]] dubbed [[Zerker]] was registered for the [[ACM 1990]] tournament, noted as promising newcomer, as it reported 7,000,000 moves per second <ref>[http://www.computerhistory.org/chess/full_record.php?iid=doc-431614f6cbb95 The 21st Annual ACM North American Computer Chess Championship] from [[The Computer History Museum]], [http://archive.computerhistory.org/projects/chess/related_materials/text/3-1%20and%203-2%20and%203-3%20and%204-3.1990_21st_NACCC/1990%20NACCC.062303065.sm.pdf pdf]</ref>, roughly three times faster than [[Deep Thought]] at that time. Unfortunately, a damage to the machine during shipment from California forced its withdrawal <ref>[http://www.thefreelibrary.com/Quick+moves+claim+computer-chess+title.-a09145976 Quick moves claim computer-chess title - Free Online Library], November 24, 1990</ref> <ref>[[Monroe Newborn|Monty Newborn]], [[Danny Kopec]] ('''1991'''). ''[http://dl.acm.org/citation.cfm?id=125497 The 21st ACM North American Computer Chess Championship]''. [[ACM#Communications|Communications of the ACM]], Vol. 34, No. 11, [http://www.accessmylibrary.com/article-1G1-11640254/21st-acm-north-american.html online]</ref>, and it seems the project was later abandoned.
=See also=
* [[Belle]]
* [[CHEOPS]]
* [[Zerker]]
=Publications=
* [[Ozalp Babaoglu]] ('''1977'''). ''Hardware implementation of the legal move generation and relative ordering functions for the game of chess''. Master's thesis, [[University of California, Berkeley]]
* [[James Testa]], [[Alvin M. Despain]] ('''1990'''). ''[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=124744&contentType=Conference+Publications&searchWithin%3Dp_Authors%3A.QT.Testa%2C+J..QT. A CMOS VLSI chess microprocessor]''. [[University of California, Berkeley]], [[IEEE]] Custom Integrated Circuit Conference
* [[Marc Boulé]] ('''2002'''). ''An FPGA Move Generator for the Game of Chess''. Masters thesis, [[McGill University]], (Supervisor: [[Zeljko Zilic]], Co-Supervisor: [[Monroe Newborn|Monty Newborn]]), [http://www.iml.ece.mcgill.ca/%7Emboule/files/mbthesis02.pdf pdf]
=References=
<references />
'''[[Hardware|Up one Level]]'''
[[FILE:CampanileMtTamalpiasSunset-original.jpg|220px|border|right|thumb| [https://en.wikipedia.org/wiki/Sather_Tower The Campanile], UC Berkeley <ref>[https://en.wikipedia.org/wiki/Sather_Tower The Campanile] and [https://en.wikipedia.org/wiki/Mount_Tamalpais Mt. Tamalpais] from [https://en.wikipedia.org/wiki/California_Memorial_Stadium Memorial Stadium] at sunset, 2006 by Tristan Harward, [https://en.wikipedia.org/wiki/University_of_California,_Berkeley University of California, Berkeley - Wikipedia]</ref>
]]
'''Berkeley Chess Microprocessor''', (BCM)<br/>
a chess microprocessor developed by [[James Testa]] and [[Alvin M. Despain]] at [[University of California, Berkeley]] <ref>[[James Testa]], [[Alvin M. Despain]] ('''1990'''). ''[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=124744&contentType=Conference+Publications&searchWithin%3Dp_Authors%3A.QT.Testa%2C+J..QT. A CMOS VLSI chess microprocessor]''. [[University of California, Berkeley]], [[IEEE]] Custom Integrated Circuit Conference</ref> , introduced in May 1990 at the ''Custom Integrated Circuits Conference'' <ref>[http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=140 Custom Integrated Circuits Conference, 1990, Proceedings of the IEEE 1990]</ref>, also mentioned in [[Marc Boulé|Marc Boulé's]] 2002 thesis <ref>[[Marc Boulé]] ('''2002'''). ''An FPGA Move Generator for the Game of Chess''. Masters thesis, [[McGill University]], (Supervisor: [[Zeljko Zilic]], Co-Supervisor: [[Monroe Newborn|Monty Newborn]]), [http://www.iml.ece.mcgill.ca/%7Emboule/files/mbthesis02.pdf pdf]</ref>.
The BCM was a 200,000 [https://en.wikipedia.org/wiki/Transistor transistor] [[VLSI Design|VLSI chip]], 1.2 [https://en.wikipedia.org/wiki/Micrometre micron] [https://en.wikipedia.org/wiki/CMOS CMOS] [https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 die], 11 mm by 9 mm in area, able to [[Move Generation|generate]] three million [[Legal Move|legal moves]] per second. The chip incorporates a move generator, a basic [[Evaluation|positional evaluator]] and [[Search|search]] control, can detect [[Pin|pins]] and [[X-ray Attacks (Bitboards)|X-ray attacks]], and has an [[Combinatorial Logic#ALU|ALU]] for each [[Squares|square]] to sum the values of attacking pieces to perform a kind of parallel [[Static Exchange Evaluation|SEE]] for [[Move Ordering|move ordering]] and [[Evaluation|evaluation]] purposes such as [[Mobility|mobility]] and [[Square Control|square control]].
=Move Generation=
While the [[Move Generation|move generation]] design is similar to [[Belle|Belle's]], legal move generation in hardware was already designed by Alvin Despain in the 70s, as described by [[Ozalp Babaoglu]] in his 1977 thesis <ref>[[Ozalp Babaoglu]] ('''1977'''). ''Hardware implementation of the legal move generation and relative ordering functions for the game of chess''. Master's thesis, [[University of California, Berkeley]]</ref> , but as noted by [[Joe Condon]] and [[Ken Thompson]], never obtained funding for full construction <ref>[[Joe Condon]], [[Ken Thompson]] ('''1982'''). ''Belle Chess Hardware''. [[Advances in Computer Chess 3]], Reprinted ('''1988''') in [[Computer Chess Compendium]]</ref> . Both, attackers and victims, emit signals in all directions simultaneously so that it is a matter of [[Combinatorial Logic|combinatorial logic]] in the square receivers to detect pins. [[Belle#FindVictim|Find victim]] and [[Belle#FindAggressor|find attacker]] cycles use programmable priority arbiters for [[Move Ordering|move ordering]] during full width as well as [[Quiescence Search|quiescence search]]. A 25–level ply [[Stack|stack]] to enable or disable [[Origin Square|origin-]] and [[Target Square|target squares]] keeps track of the move generation stage, and controls which move is generated next. This is how the bookkeeping works in sequential [[C]] like pseudo code with [[Bitboards]] (omitting legal move logic):
<pre>
disable[ply] = depth <= 0 ? emptySquares : 0; /* enable to-squares */
while ( ( to = findMVV(disable[ply])) >= 0 ) {
disable[ply] &= ~ownPieces; /* enable all possible from-squares */
while ( ( from = findLVA(disable[ply])) >= 0 ) {
make(from, to); /* ply++ */
....
unmake(from, to); /* ply-- */
disable[ply] |= 1 << from; /* disable from-square */
}
disable[ply] |= 1 << to; /* disable to-square */
}
</pre>
=Zerker=
The Berkeley Chess Microprocessor lacked participation in computer chess competitions. A chess entity of BCM's co-author [[James Testa]] dubbed [[Zerker]] was registered for the [[ACM 1990]] tournament, noted as promising newcomer, as it reported 7,000,000 moves per second <ref>[http://www.computerhistory.org/chess/full_record.php?iid=doc-431614f6cbb95 The 21st Annual ACM North American Computer Chess Championship] from [[The Computer History Museum]], [http://archive.computerhistory.org/projects/chess/related_materials/text/3-1%20and%203-2%20and%203-3%20and%204-3.1990_21st_NACCC/1990%20NACCC.062303065.sm.pdf pdf]</ref>, roughly three times faster than [[Deep Thought]] at that time. Unfortunately, a damage to the machine during shipment from California forced its withdrawal <ref>[http://www.thefreelibrary.com/Quick+moves+claim+computer-chess+title.-a09145976 Quick moves claim computer-chess title - Free Online Library], November 24, 1990</ref> <ref>[[Monroe Newborn|Monty Newborn]], [[Danny Kopec]] ('''1991'''). ''[http://dl.acm.org/citation.cfm?id=125497 The 21st ACM North American Computer Chess Championship]''. [[ACM#Communications|Communications of the ACM]], Vol. 34, No. 11, [http://www.accessmylibrary.com/article-1G1-11640254/21st-acm-north-american.html online]</ref>, and it seems the project was later abandoned.
=See also=
* [[Belle]]
* [[CHEOPS]]
* [[Zerker]]
=Publications=
* [[Ozalp Babaoglu]] ('''1977'''). ''Hardware implementation of the legal move generation and relative ordering functions for the game of chess''. Master's thesis, [[University of California, Berkeley]]
* [[James Testa]], [[Alvin M. Despain]] ('''1990'''). ''[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=124744&contentType=Conference+Publications&searchWithin%3Dp_Authors%3A.QT.Testa%2C+J..QT. A CMOS VLSI chess microprocessor]''. [[University of California, Berkeley]], [[IEEE]] Custom Integrated Circuit Conference
* [[Marc Boulé]] ('''2002'''). ''An FPGA Move Generator for the Game of Chess''. Masters thesis, [[McGill University]], (Supervisor: [[Zeljko Zilic]], Co-Supervisor: [[Monroe Newborn|Monty Newborn]]), [http://www.iml.ece.mcgill.ca/%7Emboule/files/mbthesis02.pdf pdf]
=References=
<references />
'''[[Hardware|Up one Level]]'''
