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Berkeley Chess Microprocessor

67 bytes removed, 15:33, 17 June 2018
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* [[Ozalp Babaoglu]] ('''1977'''). ''Hardware implementation of the legal move generation and relative ordering functions for the game of chess''. Master's thesis, [[University of California, Berkeley]]
* [[James Testa]], [[Alvin M. Despain]] ('''1990'''). ''[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=124744&contentType=Conference+Publications&searchWithin%3Dp_Authors%3A.QT.Testa%2C+J..QT. A CMOS VLSI chess microprocessor]''. [[University of California, Berkeley]], [[IEEE]] Custom Integrated Circuit Conference
* [[Marc Boulé]] ('''2002'''). ''An FPGA Move Generator for the Game of Chess''. Masters thesis, [[McGill University]], (Supervisor: [[Zeljko Zilic]], Co-Supervisor: [[Monroe Newborn|Monty Newborn]]), [http://www.iml.ece.mcgill.ca/%7Emboule/files/mbthesis02.pdf pdf]
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'''[[Hardware|Up one Level]]'''

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