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X86
,Created page with "'''Home * Hardware * x86''' [[FILE:Intel 80386 DX die.JPG|border|right|thumb| [https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 Die] shot of Int..."
'''[[Main Page|Home]] * [[Hardware]] * x86'''
[[FILE:Intel 80386 DX die.JPG|border|right|thumb| [https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 Die] shot of [[Intel]] 80386 DX-25 <ref>[https://commons.wikimedia.org/wiki/File:Intel_80386_DX_die.JPG Die shot] of [[Intel]] 80386 DX-25 microprocessor (SX215) by [https://commons.wikimedia.org/wiki/User:Birdman86 Pauli Rautakorpi], October 28, 2013, [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons]</ref>]]
'''x86''', <br/>
referring the [https://en.wikipedia.org/wiki/IA-32 IA-32] architecture of the 32-bit instruction set of the [[Intel]] [https://en.wikipedia.org/wiki/Intel_80386 80386] processor released in 1985 - the successor of Intel's 16-bit [[8086]] until [[80286]] processors. x86-32 could address up to 4GByte physical [[Memory|memory]], had virtual memory pages and a mode to protect them over process boundaries - a requirement for multitasking operating systems, despite 16-bit [[MS-DOS]] was still popular. While the initial x86 was [https://en.wikipedia.org/wiki/Complex_instruction_set_computer Complex Instruction Set Computing] (CISC), the [https://en.wikipedia.org/wiki/Reduced_instruction_set_computer RISC] versus CISC issue had become indistinct with more recent x86 processors, internally processing RISC like micro opcode. Over the time, modern architectural features, such as [https://en.wikipedia.org/wiki/Out-of-order_execution Out-of-order execution], [https://en.wikipedia.org/wiki/Instruction_pipeline Pipelining], [https://en.wikipedia.org/wiki/Register_renaming Register Renaming] and [https://en.wikipedia.org/wiki/Branch_predication Branch Predication] became an issue. 80386 was once clocked by about 25MHz. The [[Memory#RAM|RAM]] access speed could not keep up with higher and higher clock frequency of later processors - small but faster [https://en.wikipedia.org/wiki/CPU_cache cache memory] became necessary and strategies to make them efficient, nowadays even with three cache levels with different size and speed.
''see [[x86-64]] for x86 64-bit''
<span id="chess"></span>
=Computer Chess=
A lot of commercial and amateur [[IBM PC|PC]] chess programs, notably under the operating systems [[MS-DOS]] and later [[Windows]] and [[Linux]], were developed for this widespread architecture, often taking advantage of 32-bit registers and new instructions, for instance '''bsf''' and '''btr''' for [[BitScan|bitscanning]] 2 * 32-bit [[Bitboards]] and 32-bit [[Piece-Sets]]. Those instructions were usually not available through high level programming languages, but through [[Assembly]] language, later often as [[Assembly#InlineAssembly|inline assembly]] of various high level language compilers, for instance [https://en.wikipedia.org/wiki/Visual_C%2B%2B Microsoft Visual C] and the [[Free Software Foundation#GCC|GNU C Compiler]]. Under the 16-bit [https://en.wikipedia.org/wiki/Real_mode real mode] operating system MS-DOS, it was quite common in chess programming to use the [https://en.wikipedia.org/wiki/Unreal_mode unreal mode] <ref>[http://www.programmersheaven.com/download/1364/download.aspx Flat real / real big / unreal mode (v1.2)] from [http://www.programmersheaven.com/ Programmer's Heaven]</ref> <ref>[https://groups.google.com/group/comp.lang.asm.x86/browse_frm/thread/6ded3c0f3241b432 Unreal mode] by Safronov's family, [https://groups.google.com/group/comp.lang.asm.x86/topics comp.lang.asm.x86], June 5, 2003</ref> to allocate much more physical [[Memory|memory]] for the [[Transposition Table]], the 16 bit operating system, not aware of the huge address space, could access. Other DOS programs relied on [https://en.wikipedia.org/wiki/DOS_extender memory extenders].
=Architectures=
While the 80386 represented the third microarchitecture (after 8086, [https://en.wikipedia.org/wiki/80286 80286]), [https://en.wikipedia.org/wiki/Intel_80486 80486] and Pentium were the fourth and fifth, later called [https://en.wikipedia.org/wiki/P5_%28microarchitecture%29 P5 microarchitecture]. In 1995 with [https://en.wikipedia.org/wiki/Pentium_Pro Pentium Pro], Intel introduced the [https://en.wikipedia.org/wiki/Intel_P6_%28microarchitecture%29 P6 microarchitecture], eventually revived in the [https://en.wikipedia.org/wiki/Pentium_M Pentium M] line of microprocessors and the predecessor of Intel's [https://en.wikipedia.org/wiki/Intel_Core_2 Core 2 microarchitecture]. Intel's [https://en.wikipedia.org/wiki/Intel_NetBurst_%28microarchitecture%29 NetBurst] microarchitecture with the advent of the [https://chessprogramming.wikispaces.com/Pentium+4 Pentium 4] processor, was famous for its clock speed, but no good reputation by most chess programmers, who favored the [[AMD]] K6- and K7-architecture, namely the [https://en.wikipedia.org/wiki/Athlon Athlon] processor at that time. To begin with the rebirth of P6 and [https://en.wikipedia.org/wiki/Intel_Core_2 Intel Core 2] architecture in 2006, things changed in favor to Intel again. In November 2008 the [https://en.wikipedia.org/wiki/Nehalem_%28microarchitecture%29 Nehalem] microarchitecture appeared.
Intel's [https://en.wikipedia.org/wiki/IA-64 IA-64] architecture is a complete new and incompatible instruction set to IA-32. It is used by the [[Itanium]] line of processors. The backward compatible 64-bit successor was designed by [[AMD]] with the advent of Hammer or AMD64, later cloned by Intel and together referred to the [[x86-64]] architecture.
=Register Files=
x86 has eight 32-bit general purpose registers:
==General Purpose==
The eight general purpose registers may be treated as 32-bit [[Double Word]], 16-bit [[Word]] and high and low [[Byte]]:
{| class="wikitable"
|-
! 32
! 16
! 8 high
! 8 low
! Purpose
|-
| EAX
| AX
| AH
| AL
| GP, Accumulator
|-
| EBX
| BX
| BH
| BL
| GP, Index Register
|-
| ECX
| CX
| CH
| CL
| GP, Counter, variable shift, rotate via CL
|-
| EDX
| DX
| DH
| DL
| GP, high Accumulator mul/div
|-
| ESI
| SI
| -
| -
| GP, Source Index
|-
| EDI
| DI
| -
| -
| GP, Destination Index
|-
| ESP
| SP
| -
| -
| [[Stack|Stack Pointer]]
|-
| EBP
| BP
| -
| -
| GP, Base Pointer
|}
==MMX==
[[MMX]] was introduced with [[Intel P5 (microarchitecture)|Pentium MMX]] in 1996, adopted by [[AMD|AMD's]] [https://en.wikipedia.org/wiki/AMD_K6 K6] in 1997.
Eight 64-bit MMX-Registers: '''MM0''' - '''MM7'''.
Treated as [[Double]] or [[Quad Word]], [[Array|vector]] of two [[Float|Floats]] or [[Double Word|Double Words]], and as vector if four [[Word|Words]] or eight [[Byte|Bytes]].
==3DNow!==
An MMX-floating point extension by [[AMD]], introduced in the [https://en.wikipedia.org/wiki/AMD_K6-2 K6-2] processor, 1998.
It uses the eight 64-bit '''MMX'''-Registers: '''MM0''' - '''MM7'''.
==SSE/SSE2==
SSE was introduced by [https://en.wikipedia.org/wiki/Pentium_III Pentium III] in 1997, [[SSE2]] by [https://chessprogramming.wikispaces.com/Pentium+4 Pentium 4] in 2000
Eight 128-bit '''XMM'''-Registers: '''XMM0''' - '''XMM7'''.
Treated as [[Array|vector]] of two [[Double|Doubles]] (SSE) or [[Quad Word|Quad Words]] (SSE2), as vector of four [[Float|Floats]] (SSE) or [[Double Word|Double Words]] (SSE2), and as vector if eight [[Word|Words]] (SSE2) or 16 [[Byte|Bytes]] (SSE2).
=CPUS=
==Intel==
[[FILE:Intel Pentium P54C die.jpg|right|thumb|Pentium with P54C core <ref>Die shot of [[Intel]] Pentium with P54C core by [https://commons.wikimedia.org/wiki/User:Birdman86 Pauli Rautakorpi], June 11, 2013, [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons]</ref> ]]
* [https://en.wikipedia.org/wiki/Intel_80386 80386] 1985
* [https://en.wikipedia.org/wiki/Intel_80486 80486] 1989
* [https://en.wikipedia.org/wiki/Pentium Pentium] 1993
* [https://en.wikipedia.org/wiki/Pentium_MMX Pentium MMX] 1993
* [https://en.wikipedia.org/wiki/Intel_P6 P6 microarchitecture]
** [https://en.wikipedia.org/wiki/Pentium_Pro Pentium Pro] 1995
** [https://en.wikipedia.org/wiki/Pentium_II Pentium II] 1997
** [https://en.wikipedia.org/wiki/Pentium_III Pentium III] 1999
* [https://en.wikipedia.org/wiki/NetBurst NetBurst microarchitecture]
** [https://chessprogramming.wikispaces.com/Pentium+4 Pentium 4] 2000
* [https://en.wikipedia.org/wiki/Intel_Core_microarchitecture Intel Core microarchitecture]
** [https://en.wikipedia.org/wiki/Pentium_M Pentium M]
* <span id="Atom"></span>[https://en.wikipedia.org/wiki/Intel_Atom Intel Atom] 2008
==Cyrix==
* [https://en.wikipedia.org/wiki/Cyrix_6x86 Cyrix 6x86] 1996
==AMD==
[[FILE:AMD Athlon XP Thoroughbred die.JPG|right|thumb|AMD Athlon XP (Thoroughbred) <ref>Die shot of [[AMD]] Athlon XP microprocessor with Thoroughbred core (AXDA1800DLT3C) by [https://commons.wikimedia.org/wiki/User:Birdman86 Pauli Rautakorpi], February 14, 2014, [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons]</ref> ]]
* [https://en.wikipedia.org/wiki/AMD_K5 K5] March 1996
* [https://en.wikipedia.org/wiki/AMD_K6 K6] 1997
* [https://en.wikipedia.org/wiki/AMD_K6-2 K6-2] 1998
* [https://en.wikipedia.org/wiki/Athlon Athlon] (K7) 1999
** [https://en.wikipedia.org/wiki/Athlon#Athlon_XP.2FMP Athlon XP]
** [https://en.wikipedia.org/wiki/Athlon#Athlon_XP.2FMP Athlon MP]
: AMD has continued the name with the [https://en.wikipedia.org/wiki/Athlon_64 Athlon 64], featuring AMD64 64-bit technology, later called [[x86-64]].
=Software=
==Operating Systems==
* [[MS-DOS]]
* [[Unix]]
* [[Unix|BSD]]
* [[Linux]]
* [[Windows]]
==Development==
===Assembly===
* [[Assembly#x86|MASM]]
* [[Assembly#x86|TASM]]
===Pascal===
* [[Pascal#TurboPascal|Turbo Pascal]]
* [[Delphi]]
===C-Compiler===
* [[Turbo C]]
* [[Borland C]]
* [https://en.wikipedia.org/wiki/Visual_C%2B%2B MSVC]
* [https://en.wikipedia.org/wiki/Intel_C%2B%2B_Compiler Intel-C]
* [[Free Software Foundation#GCC|GCC]]
=Extensions=
* [[AVX]]
* [[AVX2]]
* [[AVX-512]]
* [[MMX]]
* [[SSE2]]
* [[SSE3]]
* [[SSSE3]]
* [[SSE4]]
* [[SSE5]]
* [[x86-64]]
* [[XOP]]
=Manuals=
==Intel==
* [http://flint.cs.yale.edu/cs422/doc/24547012.pdf IA-32 Intel® Architecture Software Developer’s Manual Volume 1: Basic Architecture]
* [http://flint.cs.yale.edu/cs422/doc/24547112.pdf IA-32 Intel® Architecture Software Developer’s Manual Volume 2: Instruction Set Reference]
* [http://pdos.csail.mit.edu/6.828/2006/readings/ia32/IA32-3.pdf IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide]
==AMD==
* [http://www.ii.uib.no/~osvik/amd_opt/22007k.pdf AMD Athlon Processor x86 Code Optimization Guide] (pdf)
=Forum Posts=
* [https://www.stmintz.com/ccc/index.php?id=36988 Question for Eugene Nalimov] by [[James Robertson]], [[CCC]], December 21, 1998
* [https://www.stmintz.com/ccc/index.php?id=212319 why loop unrolling isn't as useful on x86 as it once was] by [[Wylie Garvin]], [[CCC]], February 07, 2002
* [https://www.stmintz.com/ccc/index.php?id=285555 Programmer challenge] by [[Ed Schroder|Ed Schröder]], [[CCC]], February 20, 2003
* [https://www.stmintz.com/ccc/index.php?id=445557 Expert Assembler Question] by [[Ed Schroder|Ed Schröder]], [[CCC]], August 26, 2005
* [http://www.talkchess.com/forum/viewtopic.php?t=66224 Intel CPU performance-loss by security-patch?!?] by [[Stefan Pohl]], [[CCC]], January 03, 2018
=External Links=
* [https://en.wikipedia.org/wiki/X86 x86 from Wikipedia]
* [https://en.wikipedia.org/wiki/IA-32 IA-32 from Wikipedia]
* [https://en.wikipedia.org/wiki/X87 x87 from Wikipedia]
* [http://www.agner.org/optimize/#manuals Optimization manuals] by [http://www.agner.org/ Agner Fog]
* [http://www.agner.org/optimize/blog/ Agner`s CPU blog] by [http://www.agner.org/ Agner Fog]
* [http://www.intel.com/museum/online/hist%5Fmicro/hof/ Microprocessor Hall of Fame] from the [http://www.intel.com/museum/index.htm Intel Museum]
* [https://en.wikipedia.org/wiki/X86_memory_segmentation x86 memory segmentation from Wikipedia] » [[Memory]]
* [https://en.wikipedia.org/wiki/X86_calling_conventions x86 calling conventions from Wikipedia]
* [http://www.azillionmonkeys.com/qed/cpujihad.shtml 7th generation x86 CPU Comparisons] by [[Paul Hsieh]]
==Assembly==
* [http://en.wikibooks.org/wiki/X86_Assembly/X86_Architecture X86 Assembly/X86 Architecture from Wikibooks]
* [https://en.wikipedia.org/wiki/X86_assembly_language x86 assembly language from Wikipedia] » [[Assembly]]
* [https://en.wikipedia.org/wiki/X86_instruction_listings x86 instruction listings from Wikipedia]
* [http://siyobik.info/index.php?document=x86_32bit_asm x86 32-bit Assembly for Atheists]
* [http://www.cs.virginia.edu/~evans/cs216/guides/x86.html x86 Assembly Guide]
==Modes==
* [https://en.wikipedia.org/wiki/Protected_mode Protected mode from Wikipedia]
* [https://en.wikipedia.org/wiki/Real_mode Real mode from Wikipedia]
* [https://en.wikipedia.org/wiki/Unreal_mode Unreal mode from Wikipedia]
* [https://en.wikipedia.org/wiki/LOADALL LOADALL from Wikipedia]
==Instruction Sets==
* [https://en.wikipedia.org/wiki/MMX_%28instruction_set%29 MMX from Wikipedia]
* [https://en.wikipedia.org/wiki/3DNow 3DNow! from Wikipedia]
* [https://en.wikipedia.org/wiki/Streaming_SIMD_Extensions Streaming SIMD Extensions from Wikipedia]
* [https://en.wikipedia.org/wiki/SSE2 SSE2 from Wikipedia]
* [http://www.agner.org/optimize/instruction_tables.pdf Instruction Tables] (pdf) by [http://www.agner.org/ Agner Fog]
==Bugs==
* [https://en.wikipedia.org/wiki/Pentium_FDIV_bug Pentium FDIV bug from Wikipedia]
* [https://en.wikipedia.org/wiki/Pentium_F00F_bug Pentium F00F bug from Wikipedia]
==Security Vulnerability==
* [https://en.wikipedia.org/wiki/Meltdown_(security_vulnerability) Meltdown (security vulnerability) from Wikipedia]
* [https://en.wikipedia.org/wiki/Spectre_(security_vulnerability) Spectre (security vulnerability) from Wikipedia]
* [https://googleprojectzero.blogspot.de/2018/01/reading-privileged-memory-with-side.html Project Zero: Reading privileged memory with a side-channel] by [https://thejh.net/ Jann Horn], [https://en.wikipedia.org/wiki/Project_Zero Project Zero], January 03, 2018
=References=
<references />
'''[[Hardware|Up one Level]]'''
[[FILE:Intel 80386 DX die.JPG|border|right|thumb| [https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 Die] shot of [[Intel]] 80386 DX-25 <ref>[https://commons.wikimedia.org/wiki/File:Intel_80386_DX_die.JPG Die shot] of [[Intel]] 80386 DX-25 microprocessor (SX215) by [https://commons.wikimedia.org/wiki/User:Birdman86 Pauli Rautakorpi], October 28, 2013, [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons]</ref>]]
'''x86''', <br/>
referring the [https://en.wikipedia.org/wiki/IA-32 IA-32] architecture of the 32-bit instruction set of the [[Intel]] [https://en.wikipedia.org/wiki/Intel_80386 80386] processor released in 1985 - the successor of Intel's 16-bit [[8086]] until [[80286]] processors. x86-32 could address up to 4GByte physical [[Memory|memory]], had virtual memory pages and a mode to protect them over process boundaries - a requirement for multitasking operating systems, despite 16-bit [[MS-DOS]] was still popular. While the initial x86 was [https://en.wikipedia.org/wiki/Complex_instruction_set_computer Complex Instruction Set Computing] (CISC), the [https://en.wikipedia.org/wiki/Reduced_instruction_set_computer RISC] versus CISC issue had become indistinct with more recent x86 processors, internally processing RISC like micro opcode. Over the time, modern architectural features, such as [https://en.wikipedia.org/wiki/Out-of-order_execution Out-of-order execution], [https://en.wikipedia.org/wiki/Instruction_pipeline Pipelining], [https://en.wikipedia.org/wiki/Register_renaming Register Renaming] and [https://en.wikipedia.org/wiki/Branch_predication Branch Predication] became an issue. 80386 was once clocked by about 25MHz. The [[Memory#RAM|RAM]] access speed could not keep up with higher and higher clock frequency of later processors - small but faster [https://en.wikipedia.org/wiki/CPU_cache cache memory] became necessary and strategies to make them efficient, nowadays even with three cache levels with different size and speed.
''see [[x86-64]] for x86 64-bit''
<span id="chess"></span>
=Computer Chess=
A lot of commercial and amateur [[IBM PC|PC]] chess programs, notably under the operating systems [[MS-DOS]] and later [[Windows]] and [[Linux]], were developed for this widespread architecture, often taking advantage of 32-bit registers and new instructions, for instance '''bsf''' and '''btr''' for [[BitScan|bitscanning]] 2 * 32-bit [[Bitboards]] and 32-bit [[Piece-Sets]]. Those instructions were usually not available through high level programming languages, but through [[Assembly]] language, later often as [[Assembly#InlineAssembly|inline assembly]] of various high level language compilers, for instance [https://en.wikipedia.org/wiki/Visual_C%2B%2B Microsoft Visual C] and the [[Free Software Foundation#GCC|GNU C Compiler]]. Under the 16-bit [https://en.wikipedia.org/wiki/Real_mode real mode] operating system MS-DOS, it was quite common in chess programming to use the [https://en.wikipedia.org/wiki/Unreal_mode unreal mode] <ref>[http://www.programmersheaven.com/download/1364/download.aspx Flat real / real big / unreal mode (v1.2)] from [http://www.programmersheaven.com/ Programmer's Heaven]</ref> <ref>[https://groups.google.com/group/comp.lang.asm.x86/browse_frm/thread/6ded3c0f3241b432 Unreal mode] by Safronov's family, [https://groups.google.com/group/comp.lang.asm.x86/topics comp.lang.asm.x86], June 5, 2003</ref> to allocate much more physical [[Memory|memory]] for the [[Transposition Table]], the 16 bit operating system, not aware of the huge address space, could access. Other DOS programs relied on [https://en.wikipedia.org/wiki/DOS_extender memory extenders].
=Architectures=
While the 80386 represented the third microarchitecture (after 8086, [https://en.wikipedia.org/wiki/80286 80286]), [https://en.wikipedia.org/wiki/Intel_80486 80486] and Pentium were the fourth and fifth, later called [https://en.wikipedia.org/wiki/P5_%28microarchitecture%29 P5 microarchitecture]. In 1995 with [https://en.wikipedia.org/wiki/Pentium_Pro Pentium Pro], Intel introduced the [https://en.wikipedia.org/wiki/Intel_P6_%28microarchitecture%29 P6 microarchitecture], eventually revived in the [https://en.wikipedia.org/wiki/Pentium_M Pentium M] line of microprocessors and the predecessor of Intel's [https://en.wikipedia.org/wiki/Intel_Core_2 Core 2 microarchitecture]. Intel's [https://en.wikipedia.org/wiki/Intel_NetBurst_%28microarchitecture%29 NetBurst] microarchitecture with the advent of the [https://chessprogramming.wikispaces.com/Pentium+4 Pentium 4] processor, was famous for its clock speed, but no good reputation by most chess programmers, who favored the [[AMD]] K6- and K7-architecture, namely the [https://en.wikipedia.org/wiki/Athlon Athlon] processor at that time. To begin with the rebirth of P6 and [https://en.wikipedia.org/wiki/Intel_Core_2 Intel Core 2] architecture in 2006, things changed in favor to Intel again. In November 2008 the [https://en.wikipedia.org/wiki/Nehalem_%28microarchitecture%29 Nehalem] microarchitecture appeared.
Intel's [https://en.wikipedia.org/wiki/IA-64 IA-64] architecture is a complete new and incompatible instruction set to IA-32. It is used by the [[Itanium]] line of processors. The backward compatible 64-bit successor was designed by [[AMD]] with the advent of Hammer or AMD64, later cloned by Intel and together referred to the [[x86-64]] architecture.
=Register Files=
x86 has eight 32-bit general purpose registers:
==General Purpose==
The eight general purpose registers may be treated as 32-bit [[Double Word]], 16-bit [[Word]] and high and low [[Byte]]:
{| class="wikitable"
|-
! 32
! 16
! 8 high
! 8 low
! Purpose
|-
| EAX
| AX
| AH
| AL
| GP, Accumulator
|-
| EBX
| BX
| BH
| BL
| GP, Index Register
|-
| ECX
| CX
| CH
| CL
| GP, Counter, variable shift, rotate via CL
|-
| EDX
| DX
| DH
| DL
| GP, high Accumulator mul/div
|-
| ESI
| SI
| -
| -
| GP, Source Index
|-
| EDI
| DI
| -
| -
| GP, Destination Index
|-
| ESP
| SP
| -
| -
| [[Stack|Stack Pointer]]
|-
| EBP
| BP
| -
| -
| GP, Base Pointer
|}
==MMX==
[[MMX]] was introduced with [[Intel P5 (microarchitecture)|Pentium MMX]] in 1996, adopted by [[AMD|AMD's]] [https://en.wikipedia.org/wiki/AMD_K6 K6] in 1997.
Eight 64-bit MMX-Registers: '''MM0''' - '''MM7'''.
Treated as [[Double]] or [[Quad Word]], [[Array|vector]] of two [[Float|Floats]] or [[Double Word|Double Words]], and as vector if four [[Word|Words]] or eight [[Byte|Bytes]].
==3DNow!==
An MMX-floating point extension by [[AMD]], introduced in the [https://en.wikipedia.org/wiki/AMD_K6-2 K6-2] processor, 1998.
It uses the eight 64-bit '''MMX'''-Registers: '''MM0''' - '''MM7'''.
==SSE/SSE2==
SSE was introduced by [https://en.wikipedia.org/wiki/Pentium_III Pentium III] in 1997, [[SSE2]] by [https://chessprogramming.wikispaces.com/Pentium+4 Pentium 4] in 2000
Eight 128-bit '''XMM'''-Registers: '''XMM0''' - '''XMM7'''.
Treated as [[Array|vector]] of two [[Double|Doubles]] (SSE) or [[Quad Word|Quad Words]] (SSE2), as vector of four [[Float|Floats]] (SSE) or [[Double Word|Double Words]] (SSE2), and as vector if eight [[Word|Words]] (SSE2) or 16 [[Byte|Bytes]] (SSE2).
=CPUS=
==Intel==
[[FILE:Intel Pentium P54C die.jpg|right|thumb|Pentium with P54C core <ref>Die shot of [[Intel]] Pentium with P54C core by [https://commons.wikimedia.org/wiki/User:Birdman86 Pauli Rautakorpi], June 11, 2013, [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons]</ref> ]]
* [https://en.wikipedia.org/wiki/Intel_80386 80386] 1985
* [https://en.wikipedia.org/wiki/Intel_80486 80486] 1989
* [https://en.wikipedia.org/wiki/Pentium Pentium] 1993
* [https://en.wikipedia.org/wiki/Pentium_MMX Pentium MMX] 1993
* [https://en.wikipedia.org/wiki/Intel_P6 P6 microarchitecture]
** [https://en.wikipedia.org/wiki/Pentium_Pro Pentium Pro] 1995
** [https://en.wikipedia.org/wiki/Pentium_II Pentium II] 1997
** [https://en.wikipedia.org/wiki/Pentium_III Pentium III] 1999
* [https://en.wikipedia.org/wiki/NetBurst NetBurst microarchitecture]
** [https://chessprogramming.wikispaces.com/Pentium+4 Pentium 4] 2000
* [https://en.wikipedia.org/wiki/Intel_Core_microarchitecture Intel Core microarchitecture]
** [https://en.wikipedia.org/wiki/Pentium_M Pentium M]
* <span id="Atom"></span>[https://en.wikipedia.org/wiki/Intel_Atom Intel Atom] 2008
==Cyrix==
* [https://en.wikipedia.org/wiki/Cyrix_6x86 Cyrix 6x86] 1996
==AMD==
[[FILE:AMD Athlon XP Thoroughbred die.JPG|right|thumb|AMD Athlon XP (Thoroughbred) <ref>Die shot of [[AMD]] Athlon XP microprocessor with Thoroughbred core (AXDA1800DLT3C) by [https://commons.wikimedia.org/wiki/User:Birdman86 Pauli Rautakorpi], February 14, 2014, [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons]</ref> ]]
* [https://en.wikipedia.org/wiki/AMD_K5 K5] March 1996
* [https://en.wikipedia.org/wiki/AMD_K6 K6] 1997
* [https://en.wikipedia.org/wiki/AMD_K6-2 K6-2] 1998
* [https://en.wikipedia.org/wiki/Athlon Athlon] (K7) 1999
** [https://en.wikipedia.org/wiki/Athlon#Athlon_XP.2FMP Athlon XP]
** [https://en.wikipedia.org/wiki/Athlon#Athlon_XP.2FMP Athlon MP]
: AMD has continued the name with the [https://en.wikipedia.org/wiki/Athlon_64 Athlon 64], featuring AMD64 64-bit technology, later called [[x86-64]].
=Software=
==Operating Systems==
* [[MS-DOS]]
* [[Unix]]
* [[Unix|BSD]]
* [[Linux]]
* [[Windows]]
==Development==
===Assembly===
* [[Assembly#x86|MASM]]
* [[Assembly#x86|TASM]]
===Pascal===
* [[Pascal#TurboPascal|Turbo Pascal]]
* [[Delphi]]
===C-Compiler===
* [[Turbo C]]
* [[Borland C]]
* [https://en.wikipedia.org/wiki/Visual_C%2B%2B MSVC]
* [https://en.wikipedia.org/wiki/Intel_C%2B%2B_Compiler Intel-C]
* [[Free Software Foundation#GCC|GCC]]
=Extensions=
* [[AVX]]
* [[AVX2]]
* [[AVX-512]]
* [[MMX]]
* [[SSE2]]
* [[SSE3]]
* [[SSSE3]]
* [[SSE4]]
* [[SSE5]]
* [[x86-64]]
* [[XOP]]
=Manuals=
==Intel==
* [http://flint.cs.yale.edu/cs422/doc/24547012.pdf IA-32 Intel® Architecture Software Developer’s Manual Volume 1: Basic Architecture]
* [http://flint.cs.yale.edu/cs422/doc/24547112.pdf IA-32 Intel® Architecture Software Developer’s Manual Volume 2: Instruction Set Reference]
* [http://pdos.csail.mit.edu/6.828/2006/readings/ia32/IA32-3.pdf IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide]
==AMD==
* [http://www.ii.uib.no/~osvik/amd_opt/22007k.pdf AMD Athlon Processor x86 Code Optimization Guide] (pdf)
=Forum Posts=
* [https://www.stmintz.com/ccc/index.php?id=36988 Question for Eugene Nalimov] by [[James Robertson]], [[CCC]], December 21, 1998
* [https://www.stmintz.com/ccc/index.php?id=212319 why loop unrolling isn't as useful on x86 as it once was] by [[Wylie Garvin]], [[CCC]], February 07, 2002
* [https://www.stmintz.com/ccc/index.php?id=285555 Programmer challenge] by [[Ed Schroder|Ed Schröder]], [[CCC]], February 20, 2003
* [https://www.stmintz.com/ccc/index.php?id=445557 Expert Assembler Question] by [[Ed Schroder|Ed Schröder]], [[CCC]], August 26, 2005
* [http://www.talkchess.com/forum/viewtopic.php?t=66224 Intel CPU performance-loss by security-patch?!?] by [[Stefan Pohl]], [[CCC]], January 03, 2018
=External Links=
* [https://en.wikipedia.org/wiki/X86 x86 from Wikipedia]
* [https://en.wikipedia.org/wiki/IA-32 IA-32 from Wikipedia]
* [https://en.wikipedia.org/wiki/X87 x87 from Wikipedia]
* [http://www.agner.org/optimize/#manuals Optimization manuals] by [http://www.agner.org/ Agner Fog]
* [http://www.agner.org/optimize/blog/ Agner`s CPU blog] by [http://www.agner.org/ Agner Fog]
* [http://www.intel.com/museum/online/hist%5Fmicro/hof/ Microprocessor Hall of Fame] from the [http://www.intel.com/museum/index.htm Intel Museum]
* [https://en.wikipedia.org/wiki/X86_memory_segmentation x86 memory segmentation from Wikipedia] » [[Memory]]
* [https://en.wikipedia.org/wiki/X86_calling_conventions x86 calling conventions from Wikipedia]
* [http://www.azillionmonkeys.com/qed/cpujihad.shtml 7th generation x86 CPU Comparisons] by [[Paul Hsieh]]
==Assembly==
* [http://en.wikibooks.org/wiki/X86_Assembly/X86_Architecture X86 Assembly/X86 Architecture from Wikibooks]
* [https://en.wikipedia.org/wiki/X86_assembly_language x86 assembly language from Wikipedia] » [[Assembly]]
* [https://en.wikipedia.org/wiki/X86_instruction_listings x86 instruction listings from Wikipedia]
* [http://siyobik.info/index.php?document=x86_32bit_asm x86 32-bit Assembly for Atheists]
* [http://www.cs.virginia.edu/~evans/cs216/guides/x86.html x86 Assembly Guide]
==Modes==
* [https://en.wikipedia.org/wiki/Protected_mode Protected mode from Wikipedia]
* [https://en.wikipedia.org/wiki/Real_mode Real mode from Wikipedia]
* [https://en.wikipedia.org/wiki/Unreal_mode Unreal mode from Wikipedia]
* [https://en.wikipedia.org/wiki/LOADALL LOADALL from Wikipedia]
==Instruction Sets==
* [https://en.wikipedia.org/wiki/MMX_%28instruction_set%29 MMX from Wikipedia]
* [https://en.wikipedia.org/wiki/3DNow 3DNow! from Wikipedia]
* [https://en.wikipedia.org/wiki/Streaming_SIMD_Extensions Streaming SIMD Extensions from Wikipedia]
* [https://en.wikipedia.org/wiki/SSE2 SSE2 from Wikipedia]
* [http://www.agner.org/optimize/instruction_tables.pdf Instruction Tables] (pdf) by [http://www.agner.org/ Agner Fog]
==Bugs==
* [https://en.wikipedia.org/wiki/Pentium_FDIV_bug Pentium FDIV bug from Wikipedia]
* [https://en.wikipedia.org/wiki/Pentium_F00F_bug Pentium F00F bug from Wikipedia]
==Security Vulnerability==
* [https://en.wikipedia.org/wiki/Meltdown_(security_vulnerability) Meltdown (security vulnerability) from Wikipedia]
* [https://en.wikipedia.org/wiki/Spectre_(security_vulnerability) Spectre (security vulnerability) from Wikipedia]
* [https://googleprojectzero.blogspot.de/2018/01/reading-privileged-memory-with-side.html Project Zero: Reading privileged memory with a side-channel] by [https://thejh.net/ Jann Horn], [https://en.wikipedia.org/wiki/Project_Zero Project Zero], January 03, 2018
=References=
<references />
'''[[Hardware|Up one Level]]'''
