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Talk:GPU

28 bytes added, 10:18, 22 April 2021

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== AMD architectures ==

AMD has some kind of NDA in their newest whitepapers, so I will put this into the discussion section...my own conclusions are:

* TeraScale has VLIW design

* GCN has 16 wide SIMD, executing a Wavefront of 64 threads over 4 cycles.

* RDNA has 32 wide SIMD, executing a Wavefront:32 over 1 cycle and Wavefront:64 over two cycles.

[[User:Smatovic|Smatovic]] ([[User talk:Smatovic|talk]]) 10:16, 22 April 2021 (CEST)

== Nvidia architectures ==

[[User:Smatovic|Smatovic]] ([[User talk:Smatovic|talk]]) 11:48, 18 April 2021 (CEST)

~~== AMD architectures ==~~

~~AMD has some kind of NDA in their newest whitepapers, so I will put this into the discussion section...my own conclusions are:~~

* TeraScale has VLIW design

* GCN has 16 wide SIMD, executing a Wavefront of 64 threads over 4 cycles.

* RDNA has 32 wide SIMD, executing a Wavefront:32 over 1 cycle and Wavefront:64 over two cycles.

~~[[User:Smatovic|Smatovic]] ([[User talk:Smatovic|talk]])~~

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