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According to AMD papers It seems every SIMD unit has one scalar uniton GPU architectures, Nvidia seems to have SFUs, executing things like branch-conditions or special function unitsfunctions the SIMD ALUs are not capable of.

[[User:Smatovic|Smatovic]] ([[User talk:Smatovic|talk]]) 1120:4721, 18 22 April 2021 (CEST)

It is not documented in the white paperswhitepapers, but it seems that every discrete GPU has an embedded CPU controller (e.g. Nvidia Falcon) who (speculation) launches the kernels.

[[User:Smatovic|Smatovic]] ([[User talk:Smatovic|talk]]) 1110:4836, 18 22 April 2021 (CEST)

== AMD architectures CPW GPU article ==

AMD has some kind A suggestion of NDA in their newest whitepapersmine, so I will put keep this into the discussion sectionGPU article as an generalized overview of GPUs, with incremental updates for different frameworks and architectures...my GPUs and GPGPU is a moving target with different platforms offering new feature sets, better open own conclusions are: * TeraScale has VLIW design* GCN has 16 wide SIMDarticles for things like GPGPU, executing a Wavefront of 64 threads over 4 cycles.* RDNA has 32 wide SIMDSIMT, CUDA, ROCm, oneAPI, executing a Wavefront:32 over 1 cycle Metal or simply link to Wikipedia containing the newest specs and Wavefront:64 over two cyclesinfos.

[[User:Smatovic|Smatovic]] ([[User talk:Smatovic|talk]]) 21:29, 27 April 2021 (CEST)