Changes

According to AMD papers It seems every SIMD unit has one scalar uniton GPU architectures, Nvidia seems to have SFUs, executing things like branch-conditions or special function unitsfunctions the SIMD ALUs are not capable of.

[[User:Smatovic|Smatovic]] ([[User talk:Smatovic|talk]]) 1120:4721, 18 22 April 2021 (CEST)

It is not documented in the white paperswhitepapers, but it seems that every discrete GPU has an embedded CPU controller (e.g. Nvidia Falcon) who (speculation) launches the kernels.

[[User:Smatovic|Smatovic]] ([[User talk:Smatovic|talk]]) 1110:4836, 18 22 April 2021 (CEST) == AMD architectures ==

* TeraScale has VLIW design* GCN has 16 wide SIMDA suggestion of mine, executing a Wavefront keep this GPU article as an generalized overview of 64 threads over 4 cyclesGPUs, with incremental updates for different frameworks and architectures.* RDNA has 32 wide SIMDGPUs and GPGPU is a moving target with different platforms offering new feature sets, better open own articles for things like GPGPU, SIMT, CUDA, ROCm, executing a Wavefront:32 over 1 cycle oneAPI, Metal or simply link to Wikipedia containing the newest specs and Wavefront:64 over two cyclesinfos.

[[User:Smatovic|Smatovic]] ([[User talk:Smatovic|talk]]) 1021:1629, 22 27 April 2021 (CEST)