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,Created page with "'''Home * Hardware * x86 * SSE3''' '''SSE3''' (Streaming SIMD Extensions 3), is Intel's third iteration for the SSE x86 instruction set, i..."
'''[[Main Page|Home]] * [[Hardware]] * [[x86]] * SSE3'''
'''SSE3''' (Streaming SIMD Extensions 3), is [[Intel|Intel's]] third iteration for the [[SSE]] x86 instruction set, introduced in 2004 with the [https://en.wikipedia.org/wiki/List_of_Intel_Pentium_4_microprocessors#Prescott_.2890.C2.A0nm.29 Prescott] revision of the [https://en.wikipedia.org/wiki/Pentium_4 Pentium 4] CPU. In April 2005 [[AMD]] introduced a subset of SSE3 in revision E ([https://en.wikipedia.org/wiki/Athlon_64#Venice_.2890.C2.A0nm_SOI.29 Venice] and [https://en.wikipedia.org/wiki/Athlon_64#San_Diego_.2890.C2.A0nm_SOI.29_2 San Diego]) of their [https://en.wikipedia.org/wiki/Athlon_64 Athlon 64] CPUs. The 13 new instructions are most processing vectors of [[Float|floats]] or [[Double|doubles]], most notable horizontal add and sub inside one 128-bit xmm-register, LDDQU, an alternative misaligned load, which is even quite fast for loads that cross cacheline boundaries <ref>[http://siyobik.info/index.php?module=x86&id=150 LDDQU: Load Unaligned Integer 128 Bits (x86 Instruction Set Reference)]</ref><ref>[http://www.patentstorm.us/patents/6721866/description.html Unaligned memory operands - US Patent 6721866 Description]</ref>, and FISTTP, which is a new [https://en.wikipedia.org/wiki/X87 x87] instruction <ref>[http://software.intel.com/en-us/articles/how-to-implement-the-fisttp-streaming-simd-extensions-3-instruction/ How to Implement the FISTTP Streaming SIMD Extensions 3 Instruction - Intel® Software Network]</ref>.
=See also=
* [[AltiVec]]
* [[AVX]]
* [[MMX]]
* [[SIMD and SWAR Techniques]]
* [[SSE]]
* [[SSE2]]
* [[SSSE3]]
* [[SSE4]]
* [[SSE5]]
* [[x86-64]]
* [[XOP]]
=Publications=
* [[Daisuke Takahashi]] ('''2007'''). ''[https://link.springer.com/chapter/10.1007%2F978-3-540-75755-9_135 An Implementation of Parallel 1-D FFT Using SSE3 Instructions on Dual-Core Processors]''. Proc. Workshop on State-of-the-Art in Scientific and Parallel Computing, [https://en.wikipedia.org/wiki/Lecture_Notes_in_Computer_Science Lecture Notes in Computer Science], No. 4699, [https://en.wikipedia.org/wiki/Springer_Science%2BBusiness_Media Springer]
=External Links=
* [https://en.wikipedia.org/wiki/SSE3 SSE3 from Wikipedia]
* [http://stackoverflow.com/questions/661338/sse-sse2-and-sse3-for-gnu-c SSE SSE2 and SSE3 for GNU C++ - Stack Overflow]
* [http://sseplus.sourceforge.net/index.html SSEPlus Project Documentation]
* [http://software.intel.com/sites/landingpage/IntrinsicsGuide/ Intel Intrinsics Guide]
=References=
<references />
'''[[x86|Up one Level]]'''
'''SSE3''' (Streaming SIMD Extensions 3), is [[Intel|Intel's]] third iteration for the [[SSE]] x86 instruction set, introduced in 2004 with the [https://en.wikipedia.org/wiki/List_of_Intel_Pentium_4_microprocessors#Prescott_.2890.C2.A0nm.29 Prescott] revision of the [https://en.wikipedia.org/wiki/Pentium_4 Pentium 4] CPU. In April 2005 [[AMD]] introduced a subset of SSE3 in revision E ([https://en.wikipedia.org/wiki/Athlon_64#Venice_.2890.C2.A0nm_SOI.29 Venice] and [https://en.wikipedia.org/wiki/Athlon_64#San_Diego_.2890.C2.A0nm_SOI.29_2 San Diego]) of their [https://en.wikipedia.org/wiki/Athlon_64 Athlon 64] CPUs. The 13 new instructions are most processing vectors of [[Float|floats]] or [[Double|doubles]], most notable horizontal add and sub inside one 128-bit xmm-register, LDDQU, an alternative misaligned load, which is even quite fast for loads that cross cacheline boundaries <ref>[http://siyobik.info/index.php?module=x86&id=150 LDDQU: Load Unaligned Integer 128 Bits (x86 Instruction Set Reference)]</ref><ref>[http://www.patentstorm.us/patents/6721866/description.html Unaligned memory operands - US Patent 6721866 Description]</ref>, and FISTTP, which is a new [https://en.wikipedia.org/wiki/X87 x87] instruction <ref>[http://software.intel.com/en-us/articles/how-to-implement-the-fisttp-streaming-simd-extensions-3-instruction/ How to Implement the FISTTP Streaming SIMD Extensions 3 Instruction - Intel® Software Network]</ref>.
=See also=
* [[AltiVec]]
* [[AVX]]
* [[MMX]]
* [[SIMD and SWAR Techniques]]
* [[SSE]]
* [[SSE2]]
* [[SSSE3]]
* [[SSE4]]
* [[SSE5]]
* [[x86-64]]
* [[XOP]]
=Publications=
* [[Daisuke Takahashi]] ('''2007'''). ''[https://link.springer.com/chapter/10.1007%2F978-3-540-75755-9_135 An Implementation of Parallel 1-D FFT Using SSE3 Instructions on Dual-Core Processors]''. Proc. Workshop on State-of-the-Art in Scientific and Parallel Computing, [https://en.wikipedia.org/wiki/Lecture_Notes_in_Computer_Science Lecture Notes in Computer Science], No. 4699, [https://en.wikipedia.org/wiki/Springer_Science%2BBusiness_Media Springer]
=External Links=
* [https://en.wikipedia.org/wiki/SSE3 SSE3 from Wikipedia]
* [http://stackoverflow.com/questions/661338/sse-sse2-and-sse3-for-gnu-c SSE SSE2 and SSE3 for GNU C++ - Stack Overflow]
* [http://sseplus.sourceforge.net/index.html SSEPlus Project Documentation]
* [http://software.intel.com/sites/landingpage/IntrinsicsGuide/ Intel Intrinsics Guide]
=References=
<references />
'''[[x86|Up one Level]]'''
