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'''[[Main Page|Home]] * [[Hardware]] * [[PowerPC]] * AltiVec'''
'''AltiVec''', (Velocity Engine by [[Apple]] and VMX by [[IBM]])<br/>
a [[SIMD and SWAR Techniques|SIMD]] [https://en.wikipedia.org/wiki/Instruction_set instruction set] designed by Apple, IBM, and [https://en.wikipedia.org/wiki/Freescale_Semiconductor Freescale Semiconductor] (formerly [[Motorola|Motorola's]] Semiconductor Products Sector) - the [https://en.wikipedia.org/wiki/AIM_alliance AIM alliance], introduced with Motorola's [[PowerPC #G4|PowerPC G4]], and Apple's [[PowerPC #G4|PowerPC G5]], now owned by [https://en.wikipedia.org/wiki/NXP_Semiconductors NXP Semiconductors] and standard part of the [https://en.wikipedia.org/wiki/Power_Architecture#Power_ISA_v.2.03 Power ISA v.2.03]. AltiVec features 32 128-bit vector registers that represent [[Array|vectors]] of either 16 [[Byte|bytes]], eight [[Word|16-bit (half) words]] or four [[Double Word|32-bit words]] or [[Float|floats]]. Most VMX/AltiVec instructions take three register operands. AltiVec has a flexible vector permute instruction (vperm), which can take arbitrary bytes from two source registers and places them in any position in a destination register controlled by an index register <ref>[https://www.linkedin.com/in/tom-thompson-500bb7b Tom Thompson] ('''1999'''). ''[http://www.mactech.com/articles/mactech/Vol.15/15.07/AltiVecRevealed/index.html AltiVec Revealed]''. [http://www.mactech.com/ MacTech], Vol. 15, No. 7</ref>. [[Free Software Foundation#GCC|GCC]] and other compilers provide intrinsics for AltiVec instructions from [[C]] or [[Cpp|C++]] source code, or include [https://en.wikipedia.org/wiki/Automatic_vectorization auto-vectorization] <ref>[https://en.wikipedia.org/wiki/AltiVec AltiVec from Wikipedia]</ref>.
=Bitboards=
AltiVec instructions are very well suited for [[Bitboards|bitboard]] [[Fill Algorithms|fill algorithms]] and branchless [[Move Generation|move generation]] techniques à la [[DirGolem]]. Since one 128-bit AltiVec register, keeping up to two [[Bitboards|bitboards]], may treated as vector of 16 bytes, shifting techniques such as [[General Setwise Operations#OneStepOnly|one step]] in all eight directions can be done more efficiently with respect to wraps from a- to the h-file or vice versa. North and south shifts by +-8 of each bitboard can be done with one vperm-instruction simultaniously, while west and east shifts can be done by bytewise shift left/right one.
=See also=
* [[AVX]] by [[Intel]]
* [[AVX2]] by [[Intel]]
* [[AVX-512]] by [[Intel]]
* [[MMX]] on [[x86]] and [[x86-64]]
* [[SIMD and SWAR Techniques]]
* [[SSE2]], [[SSE3]], [[SSSE3]] and [[SSE4]] on [[x86]] and [[x86-64]]
* [[XOP]] by [[AMD]]
=Publications=
* [http://dblp.uni-trier.de/pers/hd/t/Tyler:Jon Jon Tyler], [http://dblp.uni-trier.de/pers/hd/l/Lent:Jeff Jeff Lent], [http://dblp.uni-trier.de/pers/hd/m/Mather:Anh Anh Mather], [http://dblp.uni-trier.de/pers/hd/n/Nguyen:Huy Huy Nguyen] ('''1999'''). ''AltiVec; Bringing Vector Technology to PowerPC Processor Family''. [http://dblp.uni-trier.de/db/conf/ipccc/ipccc1999.html#TylerLMN99 IPCCC 1999], [https://www.princeton.edu/~rblee/ELE572Papers/AltivecPerm.pdf pdf]
* [https://www.linkedin.com/in/tom-thompson-500bb7b Tom Thompson] ('''1999'''). ''[http://www.mactech.com/articles/mactech/Vol.15/15.07/AltiVecRevealed/index.html AltiVec Revealed]''. [http://www.mactech.com/ MacTech], Vol. 15, No. 7
* [https://www.researchgate.net/profile/Nicolas_Fritz2 Nicolas Fritz] ('''2009'''). ''SIMD Code Generation in Data-Parallel Programming''. Ph.D. thesis, [https://en.wikipedia.org/wiki/Saarland_University Saarland University], [http://scidok.sulb.uni-saarland.de/volltexte/2009/2563/pdf/Dissertation_9229_Frit_Nico_2009.pdf?q=ibms-cell-processor pdf]
=Manuals=
* [https://www.nxp.com/files-static/32bit/doc/ref_manual/ALTIVECPIM.pdf AltiVec Technology - Programming Interface Manual] (pdf)
* [https://www.nxp.com/docs/en/reference-manual/ALTIVECPEM.pdf AltiVec Technology - Programming Environments Manual] (pdf)
=Forum Posts=
* [https://www.stmintz.com/ccc/index.php?id=71754 G4 & AltiVec] by [[Will Singleton]], [[CCC]], October 04, 1999
* [https://www.stmintz.com/ccc/index.php?id=312343 An efficiency comparison data point for x86 vs PowerPC] by [[Steven Edwards]], [[CCC]], August 22, 2003
=External Links=
* [https://en.wikipedia.org/wiki/AltiVec AltiVec from Wikipedia]
* [https://www.nxp.com/pages/altivec-technologies:DRPPCALTVC AltiVec Technologies | NXP] by [https://en.wikipedia.org/wiki/NXP_Semiconductors NXP Semiconductors]
* [http://archive.arstechnica.com/cpu/03q1/ppc970/ppc970-0.html Inside the IBM PowerPC 970 | Part II: The Execution Core] by [http://arstechnica.com/author/hannibal/ Jon Stokes], [https://en.wikipedia.org/wiki/Ars_Technica Ars Technica]
* [http://s3.mentor.com/embedded/MEPL/index.xhtml Mentor Embedded Performance Library]
=References=
<references />
'''[[PowerPC|Up one Level]]'''
'''AltiVec''', (Velocity Engine by [[Apple]] and VMX by [[IBM]])<br/>
a [[SIMD and SWAR Techniques|SIMD]] [https://en.wikipedia.org/wiki/Instruction_set instruction set] designed by Apple, IBM, and [https://en.wikipedia.org/wiki/Freescale_Semiconductor Freescale Semiconductor] (formerly [[Motorola|Motorola's]] Semiconductor Products Sector) - the [https://en.wikipedia.org/wiki/AIM_alliance AIM alliance], introduced with Motorola's [[PowerPC #G4|PowerPC G4]], and Apple's [[PowerPC #G4|PowerPC G5]], now owned by [https://en.wikipedia.org/wiki/NXP_Semiconductors NXP Semiconductors] and standard part of the [https://en.wikipedia.org/wiki/Power_Architecture#Power_ISA_v.2.03 Power ISA v.2.03]. AltiVec features 32 128-bit vector registers that represent [[Array|vectors]] of either 16 [[Byte|bytes]], eight [[Word|16-bit (half) words]] or four [[Double Word|32-bit words]] or [[Float|floats]]. Most VMX/AltiVec instructions take three register operands. AltiVec has a flexible vector permute instruction (vperm), which can take arbitrary bytes from two source registers and places them in any position in a destination register controlled by an index register <ref>[https://www.linkedin.com/in/tom-thompson-500bb7b Tom Thompson] ('''1999'''). ''[http://www.mactech.com/articles/mactech/Vol.15/15.07/AltiVecRevealed/index.html AltiVec Revealed]''. [http://www.mactech.com/ MacTech], Vol. 15, No. 7</ref>. [[Free Software Foundation#GCC|GCC]] and other compilers provide intrinsics for AltiVec instructions from [[C]] or [[Cpp|C++]] source code, or include [https://en.wikipedia.org/wiki/Automatic_vectorization auto-vectorization] <ref>[https://en.wikipedia.org/wiki/AltiVec AltiVec from Wikipedia]</ref>.
=Bitboards=
AltiVec instructions are very well suited for [[Bitboards|bitboard]] [[Fill Algorithms|fill algorithms]] and branchless [[Move Generation|move generation]] techniques à la [[DirGolem]]. Since one 128-bit AltiVec register, keeping up to two [[Bitboards|bitboards]], may treated as vector of 16 bytes, shifting techniques such as [[General Setwise Operations#OneStepOnly|one step]] in all eight directions can be done more efficiently with respect to wraps from a- to the h-file or vice versa. North and south shifts by +-8 of each bitboard can be done with one vperm-instruction simultaniously, while west and east shifts can be done by bytewise shift left/right one.
=See also=
* [[AVX]] by [[Intel]]
* [[AVX2]] by [[Intel]]
* [[AVX-512]] by [[Intel]]
* [[MMX]] on [[x86]] and [[x86-64]]
* [[SIMD and SWAR Techniques]]
* [[SSE2]], [[SSE3]], [[SSSE3]] and [[SSE4]] on [[x86]] and [[x86-64]]
* [[XOP]] by [[AMD]]
=Publications=
* [http://dblp.uni-trier.de/pers/hd/t/Tyler:Jon Jon Tyler], [http://dblp.uni-trier.de/pers/hd/l/Lent:Jeff Jeff Lent], [http://dblp.uni-trier.de/pers/hd/m/Mather:Anh Anh Mather], [http://dblp.uni-trier.de/pers/hd/n/Nguyen:Huy Huy Nguyen] ('''1999'''). ''AltiVec; Bringing Vector Technology to PowerPC Processor Family''. [http://dblp.uni-trier.de/db/conf/ipccc/ipccc1999.html#TylerLMN99 IPCCC 1999], [https://www.princeton.edu/~rblee/ELE572Papers/AltivecPerm.pdf pdf]
* [https://www.linkedin.com/in/tom-thompson-500bb7b Tom Thompson] ('''1999'''). ''[http://www.mactech.com/articles/mactech/Vol.15/15.07/AltiVecRevealed/index.html AltiVec Revealed]''. [http://www.mactech.com/ MacTech], Vol. 15, No. 7
* [https://www.researchgate.net/profile/Nicolas_Fritz2 Nicolas Fritz] ('''2009'''). ''SIMD Code Generation in Data-Parallel Programming''. Ph.D. thesis, [https://en.wikipedia.org/wiki/Saarland_University Saarland University], [http://scidok.sulb.uni-saarland.de/volltexte/2009/2563/pdf/Dissertation_9229_Frit_Nico_2009.pdf?q=ibms-cell-processor pdf]
=Manuals=
* [https://www.nxp.com/files-static/32bit/doc/ref_manual/ALTIVECPIM.pdf AltiVec Technology - Programming Interface Manual] (pdf)
* [https://www.nxp.com/docs/en/reference-manual/ALTIVECPEM.pdf AltiVec Technology - Programming Environments Manual] (pdf)
=Forum Posts=
* [https://www.stmintz.com/ccc/index.php?id=71754 G4 & AltiVec] by [[Will Singleton]], [[CCC]], October 04, 1999
* [https://www.stmintz.com/ccc/index.php?id=312343 An efficiency comparison data point for x86 vs PowerPC] by [[Steven Edwards]], [[CCC]], August 22, 2003
=External Links=
* [https://en.wikipedia.org/wiki/AltiVec AltiVec from Wikipedia]
* [https://www.nxp.com/pages/altivec-technologies:DRPPCALTVC AltiVec Technologies | NXP] by [https://en.wikipedia.org/wiki/NXP_Semiconductors NXP Semiconductors]
* [http://archive.arstechnica.com/cpu/03q1/ppc970/ppc970-0.html Inside the IBM PowerPC 970 | Part II: The Execution Core] by [http://arstechnica.com/author/hannibal/ Jon Stokes], [https://en.wikipedia.org/wiki/Ars_Technica Ars Technica]
* [http://s3.mentor.com/embedded/MEPL/index.xhtml Mentor Embedded Performance Library]
=References=
<references />
'''[[PowerPC|Up one Level]]'''
