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'''[[Main Page|Home]] * [[Hardware]] * [[x86]] * SSE5'''
'''Streaming SIMD Extensions version 5 (SSE5)''',<br/>
was a [[x86-64]] [[SIMD and SWAR Techniques|SIMD]] instruction set extension proposed by [[AMD]] in 2007, with a bunch of very interesting instructions for high performance [[Bitboards|bitboarding]] and [[Evaluation|evaluation]]. However, after [[Intel]] declared their 256-bit wide [[AVX|Advanced Vector Extensions]] (AVX) as further SIMD extension, AMD reconsidered and replaced SSE5 with three smaller instruction set extensions [[XOP]] for vectors of integers, [https://en.wikipedia.org/wiki/FMA_instruction_set FMA4] ([https://en.wikipedia.org/wiki/Multiply-accumulate fused multiply-add] on vectors of [[Float|float]] and [[Double|double]]), and [https://en.wikipedia.org/wiki/CVT16_instruction_set CVT16] ([https://en.wikipedia.org/wiki/Half_precision Half precision floating-point format]), which retain the proposed functionality of SSE5, but encode the instructions differently for better compatibility with Intel's proposed AVX instruction set and the new [https://en.wikipedia.org/wiki/VEX_prefix VEX prefix coding scheme]. The sets are stated for introduction in AMD's new [https://en.wikipedia.org/wiki/Bulldozer_%28processor%29 Bulldozer] processor core, due for release in late 2011 on a 32nm process <ref>[http://arstechnica.com/old/content/2008/11/amd-fusion-now-pushed-back-to-2011.ars AMD Fusion now pushed back to 2011] by [http://arstechnica.com/author/joel-hruska/ Joel Hruska], November 14, 2008</ref> .
=Instructions=
Some of the new instructions are quite interesting for computer chess, with applications in evaluation and byte shuffling of bitboards. Their XOP successors still work on 128-bit XMM registers <ref>[http://support.amd.com/us/Embedded_TechDocs/43479.pdf Volume 6: 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions] (pdf)</ref>, and implicitly clear the upper 128 bit of a 256-bit YMM register. Some of the instructions, like [[XOP#VPPERM|VPPERM]], have as many as 4 operands.
* [[XOP#Instructions|XOP Instructions]]
=See Also=
* [[AltiVec]]
* [[AVX]]
* [[AVX2]]
* [[AVX-512]]
* [[SIMD and SWAR Techniques]]
* [[SSE]]
* [[SSE2]]
* [[SSE3]]
* [[SSSE3]]
* [[SSE4]]
* [[XOP]]
=External Links=
* [https://en.wikipedia.org/wiki/SSE5 SSE5 from Wikipedia]
* [http://sseplus.sourceforge.net/index.html SSEPlus Project Documentation]
* [http://www.agner.org/optimize/blog/ Agner`s CPU blog] by [http://www.agner.org/ Agner Fog]
=References=
<references />
'''[[x86|Up one Level]]'''
'''Streaming SIMD Extensions version 5 (SSE5)''',<br/>
was a [[x86-64]] [[SIMD and SWAR Techniques|SIMD]] instruction set extension proposed by [[AMD]] in 2007, with a bunch of very interesting instructions for high performance [[Bitboards|bitboarding]] and [[Evaluation|evaluation]]. However, after [[Intel]] declared their 256-bit wide [[AVX|Advanced Vector Extensions]] (AVX) as further SIMD extension, AMD reconsidered and replaced SSE5 with three smaller instruction set extensions [[XOP]] for vectors of integers, [https://en.wikipedia.org/wiki/FMA_instruction_set FMA4] ([https://en.wikipedia.org/wiki/Multiply-accumulate fused multiply-add] on vectors of [[Float|float]] and [[Double|double]]), and [https://en.wikipedia.org/wiki/CVT16_instruction_set CVT16] ([https://en.wikipedia.org/wiki/Half_precision Half precision floating-point format]), which retain the proposed functionality of SSE5, but encode the instructions differently for better compatibility with Intel's proposed AVX instruction set and the new [https://en.wikipedia.org/wiki/VEX_prefix VEX prefix coding scheme]. The sets are stated for introduction in AMD's new [https://en.wikipedia.org/wiki/Bulldozer_%28processor%29 Bulldozer] processor core, due for release in late 2011 on a 32nm process <ref>[http://arstechnica.com/old/content/2008/11/amd-fusion-now-pushed-back-to-2011.ars AMD Fusion now pushed back to 2011] by [http://arstechnica.com/author/joel-hruska/ Joel Hruska], November 14, 2008</ref> .
=Instructions=
Some of the new instructions are quite interesting for computer chess, with applications in evaluation and byte shuffling of bitboards. Their XOP successors still work on 128-bit XMM registers <ref>[http://support.amd.com/us/Embedded_TechDocs/43479.pdf Volume 6: 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions] (pdf)</ref>, and implicitly clear the upper 128 bit of a 256-bit YMM register. Some of the instructions, like [[XOP#VPPERM|VPPERM]], have as many as 4 operands.
* [[XOP#Instructions|XOP Instructions]]
=See Also=
* [[AltiVec]]
* [[AVX]]
* [[AVX2]]
* [[AVX-512]]
* [[SIMD and SWAR Techniques]]
* [[SSE]]
* [[SSE2]]
* [[SSE3]]
* [[SSSE3]]
* [[SSE4]]
* [[XOP]]
=External Links=
* [https://en.wikipedia.org/wiki/SSE5 SSE5 from Wikipedia]
* [http://sseplus.sourceforge.net/index.html SSEPlus Project Documentation]
* [http://www.agner.org/optimize/blog/ Agner`s CPU blog] by [http://www.agner.org/ Agner Fog]
=References=
<references />
'''[[x86|Up one Level]]'''
