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'''[[Main Page|Home]] * [[Hardware]] * x86-64'''
[[FILE:Quad-Core AMD Opteron processor.jpg|border|right|thumb| Quad-core [[AMD]] [https://en.wikipedia.org/wiki/Opteron Opteron] processor <ref>[https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 Die] shot of [[AMD]] [https://en.wikipedia.org/wiki/Opteron Opteron] quad-core processor, [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons]</ref>
]]
'''x86-64''' or x64,<br/>
an 64-bit [[x86]]-extension, designed by [[AMD]] as Hammer- or [https://en.wikipedia.org/wiki/Athlon_64 K8] architecture with [https://en.wikipedia.org/wiki/Athlon_64 Athlon 64] and [https://en.wikipedia.org/wiki/Opteron Opteron] cpus. It has been cloned by [[Intel]] under the name ''EMT64'' and later [https://en.wikipedia.org/wiki/X86-64#Intel_64 Intel 64]. Beside 64-bit general purpose extensions, x86-64 supports [[MMX]]-, x87- as well as the 128-bit SSE- and [[SSE2]]-instruction sets. According to the CPUID-instructions, further [[SIMD and SWAR Techniques|SIMD]] Streamig Extensions, such as [[SSE3]], [[SSSE3]] (Intel only), [[SSE4]] (Core2, [https://en.wikipedia.org/wiki/AMD_K10 K10]), [[AVX]], [[AVX2]] and [[AVX-512]], and AMD's [https://en.wikipedia.org/wiki/3DNow! 3DNow!], Enhanced 3DNow! and [[XOP]].
=Register File=
x86-64 doubles the number of [[x86]] general purpose- and XMM registers.
==General Purpose==
The 16 general purpose registers may be treated as 64 bit [[Quad Word]] ([[Bitboards|bitboard]]), 32 bit [[Double Word]], 16 bit [[Word]] and high, low [[Byte]]:
{| class="wikitable"
|-
! 64
! 32
! 16
! 8 high
! 8 low
! Purpose
|-
! RAX
| EAX
| AX
| AH
| AL
| GP, Accumulator
|-
! RBX
| EBX
| BX
| BH
| BL
| GP, Index Register
|-
! RCX
| ECX
| CX
| CH
| CL
| GP, Counter, variable shift, rotate via CL
|-
! RDX
| EDX
| DX
| DH
| DL
| GP, high Accumulator mul/div
|-
! RSI
| ESI
| SI
| -
| -
| GP, Source Index
|-
! RDI
| EDI
| DI
| -
| -
| GP, Destination Index
|-
! RSP
| ESP
| SP
| -
| -
| Stack Pointer
|-
! RBP
| EBP
| BP
| -
| -
| GP, Base Pointer
|-
! R08
| R08D
| R08W
| R08H
| R08L
| GP
|-
| ..
| ..
| ..
| ..
| ..
| GP
|-
! R15
| R15D
| R15W
| R15H
| R15L
| GP
|}
==[[MMX]]==
Eight 64-bit MMX-Registers: '''MM0''' - '''MM7'''.
Treated as [[Double]], [[Quad Word]] or vector of two [[Float|Floats]], [[Double Word|Double Words]], vector if four [[Word|Words]] or eight [[Byte|Bytes]].
==[[SSE]]/[[SSE2|SSE*]]==
Sixteen 128-bit XMM-Registers: '''XMM0''' - '''XMM15'''.
Treated as vector of two [[Double|Doubles]] or [[Quad Word|Quad Words]], as vector of four [[Float|Floats]] or [[Double Word|Double Words]], and as vector of eight [[Word|Words]] or 16 [[Byte|Bytes]].
==[[AVX]], [[AVX2]]/[[XOP]]==
[[Intel]] [https://en.wikipedia.org/wiki/Sandy_Bridge_%28microarchitecture%29 Sandy Bridge] and [[AMD]] [https://en.wikipedia.org/wiki/Bulldozer_%28processor%29 Bulldozer]
Sixteen 256-bit YMM-Registers: '''YMM0''' - '''YMM15''' (shared by XMM as lower half).
Treated as vector of four [[Double|Doubles]] or [[Quad Word|Quad Words]], as vector of eight [[Float|Floats]] or [[Double Word|Double Words]], and as vector of 15 [[Word|Words]] or 32 [[Byte|Bytes]].
==[[AVX-512]]==
[[Intel]] [https://en.wikipedia.org/wiki/Xeon_Phi Xeon Phi] (2015)
32 512-bit ZMM-Registers: '''ZMM0''' - '''ZMM31'''
Eight vector mask registers
=Instructions=
Useful instructions for [[Bitboards|bitboard-applications]] are by default not supported by high-level programming languages. Available through (inline) [[Assembly]] or compiler intrinsics of various C-Compilers <ref>[http://software.intel.com/sites/products/documentation/hpc/compilerpro/en-us/cpp/win/compiler_c/index.htm Intel(R) C++ Compiler User and Reference Guides] covers Intrinsics</ref>.
==General Purpose==
{{x86-64 Instructions}}
==Bit-Manipulation==
* [[SSE4#ABM|ABM]]
* [[BMI1]]
* [[BMI2]]
* [[TBM]]
==[[SSE2]]==
{{SSE2 Instructions]]
=Software=
==Operating Systems==
* [[Linux|Linux 64]]
* [[Unix|Tru64 UNIX]]
* [[Unix|BSD]]
* [[Mac OS|Mac OS X]]
* [[Windows|Windows 64]]
* [[Unix|Solaris]]
==Development==
===Assembly===
* [[Assembly#x86|MASM64]]
* [[Assembly#x86|GNU Assembler]]
===C-Compiler===
* [https://en.wikipedia.org/wiki/Microsoft_Visual_C%2B%2B Microsoft Visual C++]
* [https://en.wikipedia.org/wiki/Intel_C%2B%2B_Compiler Intel-C]
* [[Free Software Foundation#GCC|GCC]]
=See also=
* [[asmFish]]
* [[AVX]]
* [[AVX2]]
* [[AVX-512]]
* [[Bitboards]]
: [[General Setwise Operations]]
: [[BitScan]]
* [[BMI1]]
* [[BMI2]]
* [[Itanium]]
* [[NUMA]]
* [[SIMD and SWAR Techniques]]
* [[SMP]]
* [[SSE2]]
* [[SSE3]]
* [[SSSE3]]
* [[SSE4]]
* [[SSE5]]
* [[x86]]
* [[TBM]]
* [[XOP]]
=Publications=
* [https://www.rrze.fau.de/wir-ueber-uns/organigramm/mitarbeiter/index.shtml/georg-hager.shtml Georg Hager] <ref>[https://blogs.fau.de/hager/ Georg Hager's Blog | Random thoughts on High Performance Computing]</ref>, [http://dblp.uni-trier.de/pers/hd/t/Treibig:Jan Jan Treibig], [http://dblp.uni-trier.de/pers/hd/w/Wellein:Gerhard Gerhard Wellein] ('''2013'''). ''The Practitioner's Cookbook for Good Parallel Performance on Multi- and Many-Core Systems''. [https://de.wikipedia.org/wiki/Regionales_Rechenzentrum_Erlangen RRZE], [http://sc13.supercomputing.org/ SC13], [https://blogs.fau.de/hager/files/2013/11/sc13_tutorial_134.pdf slides as pdf]
* [[S. Ali Mirsoleimani]], [[Aske Plaat]], [[Jaap van den Herik]], [[Jos Vermaseren]] ('''2014'''). ''Performance analysis of a 240 thread tournament level MCTS Go program on the Intel Xeon Phi''. [http://arxiv.org/abs/1409.4297 CoRR abs/1409.4297] » [[Go]]
* [[S. Ali Mirsoleimani]], [[Aske Plaat]], [[Jaap van den Herik]], [[Jos Vermaseren]] ('''2015'''). ''Scaling Monte Carlo Tree Search on Intel Xeon Phi''. [http://arxiv.org/abs/1507.04383 CoRR abs/1507.04383] » [[Hex]], [[Monte-Carlo Tree Search|MCTS]], [[Parallel Search]]
<span id="Manuals"></span>
=Manuals=
==Agner Fog==
* [http://www.agner.org/optimize/#manuals Agner Fog's manuals]
* [http://www.agner.org/optimize/blog/ Agner`s CPU blog] by [http://www.agner.org/ Agner Fog]
==AMD==
* [http://developer.amd.com/resources/developer-guides-manuals/ AMD Tech Docs]
===Instructions===
* [http://support.amd.com/TechDocs/24592.pdf Volume 1: Application Programming] (pdf)
* [http://support.amd.com/TechDocs/24593.pdf Volume 2: System Programming] (pdf)
* [http://support.amd.com/TechDocs/24594.pdf Volume 3: General-Purpose and System Instructions] (pdf)
* [http://support.amd.com/TechDocs/26568.pdf Volume 4: 128-Bit and 256-Bit Media Instructions] (pdf)
* [http://support.amd.com/TechDocs/26569_APM_v5.pdf Volume 5: 64-Bit Media and x87 Floating-Point Instructions] (pdf)
===Optimization Guides===
* [http://support.amd.com/TechDocs/25112.PDF Software Optimization Guide for AMD64 Processors] (pdf)
* [http://support.amd.com/TechDocs/47414_15h_sw_opt_guide.pdf Software Optimization Guide for AMD Family 15h Processors] (pdf)
* [http://support.amd.com/TechDocs/40555.pdf Performance Guidelines for AMD Athlon™ 64 and AMD Opteron™ ccNUMA Multiprocessor Systems] (pdf)
==Intel==
===Instructions===
* [http://www.intel.com/Assets/PDF/manual/253666.pdf Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M] (pdf)
* [http://www.intel.com/Assets/PDF/manual/253667.pdf Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z] (pdf)
* [http://software.intel.com/file/36945 Intel-AVX-Programming-Reference] (pdf)
===Optimization Guides===
* [https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf Intel® 64 and IA-32 Architectures Optimization Reference Manual] (pdf) v
=Forum Posts=
* [https://www.stmintz.com/ccc/index.php?id=283740 IA-64 vs OOOE (attn Taylor, Hyatt)] by [[Tom Kerrigan]], [[CCC]], February 11, 2003 » [[Itanium]]
* [https://www.stmintz.com/ccc/index.php?id=410357 Opteron NUMA/SMP question] by Matthew Hull, [[CCC]], February 09, 2005 » [[NUMA]], [[SMP]]
* [http://www.talkchess.com/forum/viewtopic.php?t=26542 core2 popcnt] by [[Frank Phillips]], [[CCC]], February 13, 2009 » [[Population Count]]
* [http://www.talkchess.com/forum/viewtopic.php?t=45167 Ivy Bridge vs Sandy Bridge for computer chess] by [[Larry Kaufman]], [[CCC]], September 15, 2012
* [http://www.talkchess.com/forum/viewtopic.php?t=45707 What is your take on AMD's new processor?] by Tano-Urayoan Russi Roman, [[CCC]], October 24, 2012
* [http://www.talkchess.com/forum/viewtopic.php?t=51087 Intel i3 L2 cache] by [[Harm Geert Muller]], [[CCC]], January 28, 2014 » [[Memory]] <ref>[https://en.wikipedia.org/wiki/Intel_Core#Core_i3 Intel Nehalem Core i3]</ref>
* [http://www.talkchess.com/forum/viewtopic.php?t=51996 Core Port Saturation] by [[Natale Galioto]], [[CCC]], April 14, 2014
* [http://www.talkchess.com/forum/viewtopic.php?t=61559 syzygy users (and Ronald)] by [[Robert Hyatt]], [[CCC]], September 29, 2016 » [[BitScan]], [[Population Count]]
* [https://groups.google.com/d/msg/computer-go-archive/mXE2UsBDeyA/ljUckKn-AgAJ New AMD processors] by [[Ingo Althöfer]], [http://computer-go.org/pipermail/computer-go/ The Computer-go Archives], March 03, 2017
* [https://www.reddit.com/r/Amd/comments/60i6er/ryzen_and_bmi2_strange_behavior_and_high_latencies/ Ryzen and BMI2: Strange behavior and high latencies] by DonnieTinyHands, [https://en.wikipedia.org/wiki/Reddit Reddit], March 20, 2017 » [[AMD]], [[BMI2]]
* [http://www.talkchess.com/forum/viewtopic.php?t=63564 Is anyone here already using a Ryzen 1800X processor ?] by Aloisio Ponti, [[CCC]], March 26, 2017 » [[AMD]]
* [http://www.talkchess.com/forum/viewtopic.php?t=66224 Intel CPU performance-loss by security-patch?!?] by [[Stefan Pohl]], [[CCC]], January 03, 2018
* [http://www.talkchess.com/forum/viewtopic.php?t=66737&start=4 Re: Komodo 11.3] by [[Mark Lefler]], [[CCC]], March 04, 2018 » [[AMD]], [[BMI2#PEXT|BMI2 PEXT]], [[Komodo#11|Komodo 11.3]]
=External Links=
* [https://en.wikipedia.org/wiki/X86-64 x86-64 from Wikipedia]
* [https://en.wikipedia.org/wiki/X86_calling_conventions#x86-64_calling_conventions x86-64 calling conventions from Wikipedia]
* [https://en.wikipedia.org/wiki/X86#Addressing_modes x86 Addressing modes from Wikipedia]
* [https://en.wikipedia.org/wiki/X32_ABI X32 ABI from Wikipedia] <ref>[https://en.wikipedia.org/wiki/Application_binary_interface Application binary interface from Wikipedia]</ref>
* [http://eli.thegreenplace.net/2011/09/06/stack-frame-layout-on-x86-64/ Stack frame layout on x86-64] from [http://eli.thegreenplace.net/ Eli Bendersky's website], September 06, 2011 » [[Stack]]
* [http://software.intel.com/en-us/articles/introduction-to-x64-assembly Introduction to x64 Assembly] by [http://www.lomont.org/ Chris Lomont], March 2012
==AMD==
* [https://en.wikipedia.org/wiki/AMD_K8 AMD K8 from Wikipedia]
** [https://en.wikipedia.org/wiki/Athlon_64 Athlon 64]
** [https://en.wikipedia.org/wiki/Athlon_64#Athlon_64_FX Athlon 64 FX]
** [https://en.wikipedia.org/wiki/Opteron Opteron]
** [https://en.wikipedia.org/wiki/Athlon_64_X2 Athlon 64 X2] dual-core
** [https://en.wikipedia.org/wiki/AMD_Turion#Turion_64_X2 Turion 64 X2] dual-core
* [http://arstechnica.com/articles/paedia/cpu/amd-hammer-1.ars Inside AMD's Hammer: the 64-bit architecture behind the Opteron and Athlon 64] by Jon Stokes, [http://arstechnica.com/index.ars ars technica], February 01, 2005
* [http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html Understanding the detailed Architecture of AMD's 64 bit Core] by [http://www.chip-architect.com/ Hans de Vries], September 21, 2003
* [http://www.7-cpu.com/cpu/K8.html AMD K8] from [http://www.7-cpu.com/ 7-Zip LZMA Benchmark]
* [https://en.wikipedia.org/wiki/AMD_K9 AMD K9 from Wikipedia]
* [https://en.wikipedia.org/wiki/AMD_10h AMD 10h from Wikipedia]
* [http://www.7-cpu.com/cpu/K10.html AMD K10 (Phenom)] from [http://www.7-cpu.com/ 7-Zip LZMA Benchmark]
* [https://en.wikipedia.org/wiki/Phenom_%28processor%29 Phenom] triple-core, quad-core
* [https://en.wikipedia.org/wiki/Bobcat_%28microarchitecture%29 Bobcat (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Bulldozer_%28microarchitecture%29 Bulldozer (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29 Piledriver (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Steamroller_%28microarchitecture%29 Steamroller (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Excavator_%28microarchitecture%29 Excavator (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Zen_(microarchitecture) Zen (microarchitecture) from Wikipedia]
==Intel==
* [https://en.wikipedia.org/wiki/X86-64#Intel_64 EMT64 from Wikipedia]
* [https://en.wikipedia.org/wiki/Tick-Tock_model Tick-Tock model from Wikipedia]
* [https://en.wikipedia.org/wiki/Intel_Core_%28microarchitecture%29 Intel Core (microarchitecture from Wikipedia]
* <span id="Atom"></span>[https://en.wikipedia.org/wiki/Intel_Atom Intel Atom from Wikipedia]
* [https://en.wikipedia.org/wiki/Nehalem_%28microarchitecture%29 Nehalem (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Sandy_Bridge_%28microarchitecture%29 Sandy Bridge (microarchitecture) from Wikipedia]
* [http://www.7-cpu.com/cpu/SandyBridge.html Intel Sandy Bridge] from [http://www.7-cpu.com/ 7-Zip LZMA Benchmark]
* [https://en.wikipedia.org/wiki/Ivy_Bridge_%28microarchitecture%29 Ivy Bridge (microarchitecture) from Wikipedia]
* [http://www.7-cpu.com/cpu/IvyBridge.html Intel Ivy Bridge] from [http://www.7-cpu.com/ 7-Zip LZMA Benchmark]
* [https://en.wikipedia.org/wiki/Haswell_%28microarchitecture%29 Haswell (microarchitecture) from Wikipedia]
* [http://www.7-cpu.com/cpu/Haswell.html Intel Haswell] from [http://www.7-cpu.com/ 7-Zip LZMA Benchmark]
* [http://www.realworldtech.com/haswell-cpu/ Intel's Haswell CPU Microarchitecture] by [http://www.realworldtech.com/author/dkanter/ David Kanter], November 13, 2012
* [https://en.wikipedia.org/wiki/Broadwell_%28microarchitecture%29 Broadwell (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Skylake_%28microarchitecture%29 Skylake (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Kaby_Lake Kaby Lake from Wikipedia]
* [https://en.wikipedia.org/wiki/Xeon_Phi Xeon Phi from Wikipedia]
==Instruction Sets==
* [https://en.wikipedia.org/wiki/X87 x87 from Wikipedia]
* [https://en.wikipedia.org/wiki/MMX_%28instruction_set%29 MMX from Wikipedia]
* [https://en.wikipedia.org/wiki/3DNow 3DNow! from Wikipedia]
* [https://en.wikipedia.org/wiki/Streaming_SIMD_Extensions Streaming SIMD Extensions from Wikipedia]
* [https://en.wikipedia.org/wiki/SSE2 SSE2 from Wikipedia] » [[SSE2]]
* [https://en.wikipedia.org/wiki/SSE3 SSE3 from Wikipedia] » [[SSE3]]
* [https://en.wikipedia.org/wiki/SSSE3 SSSE3 from Wikipedia] » [[SSSE3]]
* [https://en.wikipedia.org/wiki/SSE4 SSE4 from Wikipedia] » [[SSE4]]
* [http://de.wikipedia.org/wiki/SSE4a SSE4a from Wikipedia]
* [https://en.wikipedia.org/wiki/SSE5 SSE5 from Wikipedia] » [[SSE5]]
* [https://en.wikipedia.org/wiki/XOP_instruction_set XOP instruction set from Wikipedia] » [[XOP]]
* [https://en.wikipedia.org/wiki/Advanced_Vector_Extensions Advanced Vector Extensions (AVX) from Wikipedia] » [[AVX]]
: [https://en.wikipedia.org/wiki/AVX-512 AVX-512 from Wikipedia] » [[AVX-512]]
* [https://en.wikipedia.org/wiki/Transactional_Synchronization_Extensions Transactional Synchronization Extensions (TSX) from Wikipedia] ([https://en.wikipedia.org/wiki/Haswell_%28microarchitecture%29 Haswell])
* [http://software.intel.com/sites/landingpage/IntrinsicsGuide/ Intel Intrinsics Guide]
==Security Vulnerability==
* [https://en.wikipedia.org/wiki/Meltdown_(security_vulnerability) Meltdown (security vulnerability) from Wikipedia]
* [https://en.wikipedia.org/wiki/Spectre_(security_vulnerability) Spectre (security vulnerability) from Wikipedia]
* [https://googleprojectzero.blogspot.de/2018/01/reading-privileged-memory-with-side.html Project Zero: Reading privileged memory with a side-channel] by [https://thejh.net/ Jann Horn], [https://en.wikipedia.org/wiki/Project_Zero Project Zero], January 03, 2018
=References=
<references />
'''[[Hardware|Up one Level]]'''
[[FILE:Quad-Core AMD Opteron processor.jpg|border|right|thumb| Quad-core [[AMD]] [https://en.wikipedia.org/wiki/Opteron Opteron] processor <ref>[https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 Die] shot of [[AMD]] [https://en.wikipedia.org/wiki/Opteron Opteron] quad-core processor, [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons]</ref>
]]
'''x86-64''' or x64,<br/>
an 64-bit [[x86]]-extension, designed by [[AMD]] as Hammer- or [https://en.wikipedia.org/wiki/Athlon_64 K8] architecture with [https://en.wikipedia.org/wiki/Athlon_64 Athlon 64] and [https://en.wikipedia.org/wiki/Opteron Opteron] cpus. It has been cloned by [[Intel]] under the name ''EMT64'' and later [https://en.wikipedia.org/wiki/X86-64#Intel_64 Intel 64]. Beside 64-bit general purpose extensions, x86-64 supports [[MMX]]-, x87- as well as the 128-bit SSE- and [[SSE2]]-instruction sets. According to the CPUID-instructions, further [[SIMD and SWAR Techniques|SIMD]] Streamig Extensions, such as [[SSE3]], [[SSSE3]] (Intel only), [[SSE4]] (Core2, [https://en.wikipedia.org/wiki/AMD_K10 K10]), [[AVX]], [[AVX2]] and [[AVX-512]], and AMD's [https://en.wikipedia.org/wiki/3DNow! 3DNow!], Enhanced 3DNow! and [[XOP]].
=Register File=
x86-64 doubles the number of [[x86]] general purpose- and XMM registers.
==General Purpose==
The 16 general purpose registers may be treated as 64 bit [[Quad Word]] ([[Bitboards|bitboard]]), 32 bit [[Double Word]], 16 bit [[Word]] and high, low [[Byte]]:
{| class="wikitable"
|-
! 64
! 32
! 16
! 8 high
! 8 low
! Purpose
|-
! RAX
| EAX
| AX
| AH
| AL
| GP, Accumulator
|-
! RBX
| EBX
| BX
| BH
| BL
| GP, Index Register
|-
! RCX
| ECX
| CX
| CH
| CL
| GP, Counter, variable shift, rotate via CL
|-
! RDX
| EDX
| DX
| DH
| DL
| GP, high Accumulator mul/div
|-
! RSI
| ESI
| SI
| -
| -
| GP, Source Index
|-
! RDI
| EDI
| DI
| -
| -
| GP, Destination Index
|-
! RSP
| ESP
| SP
| -
| -
| Stack Pointer
|-
! RBP
| EBP
| BP
| -
| -
| GP, Base Pointer
|-
! R08
| R08D
| R08W
| R08H
| R08L
| GP
|-
| ..
| ..
| ..
| ..
| ..
| GP
|-
! R15
| R15D
| R15W
| R15H
| R15L
| GP
|}
==[[MMX]]==
Eight 64-bit MMX-Registers: '''MM0''' - '''MM7'''.
Treated as [[Double]], [[Quad Word]] or vector of two [[Float|Floats]], [[Double Word|Double Words]], vector if four [[Word|Words]] or eight [[Byte|Bytes]].
==[[SSE]]/[[SSE2|SSE*]]==
Sixteen 128-bit XMM-Registers: '''XMM0''' - '''XMM15'''.
Treated as vector of two [[Double|Doubles]] or [[Quad Word|Quad Words]], as vector of four [[Float|Floats]] or [[Double Word|Double Words]], and as vector of eight [[Word|Words]] or 16 [[Byte|Bytes]].
==[[AVX]], [[AVX2]]/[[XOP]]==
[[Intel]] [https://en.wikipedia.org/wiki/Sandy_Bridge_%28microarchitecture%29 Sandy Bridge] and [[AMD]] [https://en.wikipedia.org/wiki/Bulldozer_%28processor%29 Bulldozer]
Sixteen 256-bit YMM-Registers: '''YMM0''' - '''YMM15''' (shared by XMM as lower half).
Treated as vector of four [[Double|Doubles]] or [[Quad Word|Quad Words]], as vector of eight [[Float|Floats]] or [[Double Word|Double Words]], and as vector of 15 [[Word|Words]] or 32 [[Byte|Bytes]].
==[[AVX-512]]==
[[Intel]] [https://en.wikipedia.org/wiki/Xeon_Phi Xeon Phi] (2015)
32 512-bit ZMM-Registers: '''ZMM0''' - '''ZMM31'''
Eight vector mask registers
=Instructions=
Useful instructions for [[Bitboards|bitboard-applications]] are by default not supported by high-level programming languages. Available through (inline) [[Assembly]] or compiler intrinsics of various C-Compilers <ref>[http://software.intel.com/sites/products/documentation/hpc/compilerpro/en-us/cpp/win/compiler_c/index.htm Intel(R) C++ Compiler User and Reference Guides] covers Intrinsics</ref>.
==General Purpose==
{{x86-64 Instructions}}
==Bit-Manipulation==
* [[SSE4#ABM|ABM]]
* [[BMI1]]
* [[BMI2]]
* [[TBM]]
==[[SSE2]]==
{{SSE2 Instructions]]
=Software=
==Operating Systems==
* [[Linux|Linux 64]]
* [[Unix|Tru64 UNIX]]
* [[Unix|BSD]]
* [[Mac OS|Mac OS X]]
* [[Windows|Windows 64]]
* [[Unix|Solaris]]
==Development==
===Assembly===
* [[Assembly#x86|MASM64]]
* [[Assembly#x86|GNU Assembler]]
===C-Compiler===
* [https://en.wikipedia.org/wiki/Microsoft_Visual_C%2B%2B Microsoft Visual C++]
* [https://en.wikipedia.org/wiki/Intel_C%2B%2B_Compiler Intel-C]
* [[Free Software Foundation#GCC|GCC]]
=See also=
* [[asmFish]]
* [[AVX]]
* [[AVX2]]
* [[AVX-512]]
* [[Bitboards]]
: [[General Setwise Operations]]
: [[BitScan]]
* [[BMI1]]
* [[BMI2]]
* [[Itanium]]
* [[NUMA]]
* [[SIMD and SWAR Techniques]]
* [[SMP]]
* [[SSE2]]
* [[SSE3]]
* [[SSSE3]]
* [[SSE4]]
* [[SSE5]]
* [[x86]]
* [[TBM]]
* [[XOP]]
=Publications=
* [https://www.rrze.fau.de/wir-ueber-uns/organigramm/mitarbeiter/index.shtml/georg-hager.shtml Georg Hager] <ref>[https://blogs.fau.de/hager/ Georg Hager's Blog | Random thoughts on High Performance Computing]</ref>, [http://dblp.uni-trier.de/pers/hd/t/Treibig:Jan Jan Treibig], [http://dblp.uni-trier.de/pers/hd/w/Wellein:Gerhard Gerhard Wellein] ('''2013'''). ''The Practitioner's Cookbook for Good Parallel Performance on Multi- and Many-Core Systems''. [https://de.wikipedia.org/wiki/Regionales_Rechenzentrum_Erlangen RRZE], [http://sc13.supercomputing.org/ SC13], [https://blogs.fau.de/hager/files/2013/11/sc13_tutorial_134.pdf slides as pdf]
* [[S. Ali Mirsoleimani]], [[Aske Plaat]], [[Jaap van den Herik]], [[Jos Vermaseren]] ('''2014'''). ''Performance analysis of a 240 thread tournament level MCTS Go program on the Intel Xeon Phi''. [http://arxiv.org/abs/1409.4297 CoRR abs/1409.4297] » [[Go]]
* [[S. Ali Mirsoleimani]], [[Aske Plaat]], [[Jaap van den Herik]], [[Jos Vermaseren]] ('''2015'''). ''Scaling Monte Carlo Tree Search on Intel Xeon Phi''. [http://arxiv.org/abs/1507.04383 CoRR abs/1507.04383] » [[Hex]], [[Monte-Carlo Tree Search|MCTS]], [[Parallel Search]]
<span id="Manuals"></span>
=Manuals=
==Agner Fog==
* [http://www.agner.org/optimize/#manuals Agner Fog's manuals]
* [http://www.agner.org/optimize/blog/ Agner`s CPU blog] by [http://www.agner.org/ Agner Fog]
==AMD==
* [http://developer.amd.com/resources/developer-guides-manuals/ AMD Tech Docs]
===Instructions===
* [http://support.amd.com/TechDocs/24592.pdf Volume 1: Application Programming] (pdf)
* [http://support.amd.com/TechDocs/24593.pdf Volume 2: System Programming] (pdf)
* [http://support.amd.com/TechDocs/24594.pdf Volume 3: General-Purpose and System Instructions] (pdf)
* [http://support.amd.com/TechDocs/26568.pdf Volume 4: 128-Bit and 256-Bit Media Instructions] (pdf)
* [http://support.amd.com/TechDocs/26569_APM_v5.pdf Volume 5: 64-Bit Media and x87 Floating-Point Instructions] (pdf)
===Optimization Guides===
* [http://support.amd.com/TechDocs/25112.PDF Software Optimization Guide for AMD64 Processors] (pdf)
* [http://support.amd.com/TechDocs/47414_15h_sw_opt_guide.pdf Software Optimization Guide for AMD Family 15h Processors] (pdf)
* [http://support.amd.com/TechDocs/40555.pdf Performance Guidelines for AMD Athlon™ 64 and AMD Opteron™ ccNUMA Multiprocessor Systems] (pdf)
==Intel==
===Instructions===
* [http://www.intel.com/Assets/PDF/manual/253666.pdf Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M] (pdf)
* [http://www.intel.com/Assets/PDF/manual/253667.pdf Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z] (pdf)
* [http://software.intel.com/file/36945 Intel-AVX-Programming-Reference] (pdf)
===Optimization Guides===
* [https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf Intel® 64 and IA-32 Architectures Optimization Reference Manual] (pdf) v
=Forum Posts=
* [https://www.stmintz.com/ccc/index.php?id=283740 IA-64 vs OOOE (attn Taylor, Hyatt)] by [[Tom Kerrigan]], [[CCC]], February 11, 2003 » [[Itanium]]
* [https://www.stmintz.com/ccc/index.php?id=410357 Opteron NUMA/SMP question] by Matthew Hull, [[CCC]], February 09, 2005 » [[NUMA]], [[SMP]]
* [http://www.talkchess.com/forum/viewtopic.php?t=26542 core2 popcnt] by [[Frank Phillips]], [[CCC]], February 13, 2009 » [[Population Count]]
* [http://www.talkchess.com/forum/viewtopic.php?t=45167 Ivy Bridge vs Sandy Bridge for computer chess] by [[Larry Kaufman]], [[CCC]], September 15, 2012
* [http://www.talkchess.com/forum/viewtopic.php?t=45707 What is your take on AMD's new processor?] by Tano-Urayoan Russi Roman, [[CCC]], October 24, 2012
* [http://www.talkchess.com/forum/viewtopic.php?t=51087 Intel i3 L2 cache] by [[Harm Geert Muller]], [[CCC]], January 28, 2014 » [[Memory]] <ref>[https://en.wikipedia.org/wiki/Intel_Core#Core_i3 Intel Nehalem Core i3]</ref>
* [http://www.talkchess.com/forum/viewtopic.php?t=51996 Core Port Saturation] by [[Natale Galioto]], [[CCC]], April 14, 2014
* [http://www.talkchess.com/forum/viewtopic.php?t=61559 syzygy users (and Ronald)] by [[Robert Hyatt]], [[CCC]], September 29, 2016 » [[BitScan]], [[Population Count]]
* [https://groups.google.com/d/msg/computer-go-archive/mXE2UsBDeyA/ljUckKn-AgAJ New AMD processors] by [[Ingo Althöfer]], [http://computer-go.org/pipermail/computer-go/ The Computer-go Archives], March 03, 2017
* [https://www.reddit.com/r/Amd/comments/60i6er/ryzen_and_bmi2_strange_behavior_and_high_latencies/ Ryzen and BMI2: Strange behavior and high latencies] by DonnieTinyHands, [https://en.wikipedia.org/wiki/Reddit Reddit], March 20, 2017 » [[AMD]], [[BMI2]]
* [http://www.talkchess.com/forum/viewtopic.php?t=63564 Is anyone here already using a Ryzen 1800X processor ?] by Aloisio Ponti, [[CCC]], March 26, 2017 » [[AMD]]
* [http://www.talkchess.com/forum/viewtopic.php?t=66224 Intel CPU performance-loss by security-patch?!?] by [[Stefan Pohl]], [[CCC]], January 03, 2018
* [http://www.talkchess.com/forum/viewtopic.php?t=66737&start=4 Re: Komodo 11.3] by [[Mark Lefler]], [[CCC]], March 04, 2018 » [[AMD]], [[BMI2#PEXT|BMI2 PEXT]], [[Komodo#11|Komodo 11.3]]
=External Links=
* [https://en.wikipedia.org/wiki/X86-64 x86-64 from Wikipedia]
* [https://en.wikipedia.org/wiki/X86_calling_conventions#x86-64_calling_conventions x86-64 calling conventions from Wikipedia]
* [https://en.wikipedia.org/wiki/X86#Addressing_modes x86 Addressing modes from Wikipedia]
* [https://en.wikipedia.org/wiki/X32_ABI X32 ABI from Wikipedia] <ref>[https://en.wikipedia.org/wiki/Application_binary_interface Application binary interface from Wikipedia]</ref>
* [http://eli.thegreenplace.net/2011/09/06/stack-frame-layout-on-x86-64/ Stack frame layout on x86-64] from [http://eli.thegreenplace.net/ Eli Bendersky's website], September 06, 2011 » [[Stack]]
* [http://software.intel.com/en-us/articles/introduction-to-x64-assembly Introduction to x64 Assembly] by [http://www.lomont.org/ Chris Lomont], March 2012
==AMD==
* [https://en.wikipedia.org/wiki/AMD_K8 AMD K8 from Wikipedia]
** [https://en.wikipedia.org/wiki/Athlon_64 Athlon 64]
** [https://en.wikipedia.org/wiki/Athlon_64#Athlon_64_FX Athlon 64 FX]
** [https://en.wikipedia.org/wiki/Opteron Opteron]
** [https://en.wikipedia.org/wiki/Athlon_64_X2 Athlon 64 X2] dual-core
** [https://en.wikipedia.org/wiki/AMD_Turion#Turion_64_X2 Turion 64 X2] dual-core
* [http://arstechnica.com/articles/paedia/cpu/amd-hammer-1.ars Inside AMD's Hammer: the 64-bit architecture behind the Opteron and Athlon 64] by Jon Stokes, [http://arstechnica.com/index.ars ars technica], February 01, 2005
* [http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html Understanding the detailed Architecture of AMD's 64 bit Core] by [http://www.chip-architect.com/ Hans de Vries], September 21, 2003
* [http://www.7-cpu.com/cpu/K8.html AMD K8] from [http://www.7-cpu.com/ 7-Zip LZMA Benchmark]
* [https://en.wikipedia.org/wiki/AMD_K9 AMD K9 from Wikipedia]
* [https://en.wikipedia.org/wiki/AMD_10h AMD 10h from Wikipedia]
* [http://www.7-cpu.com/cpu/K10.html AMD K10 (Phenom)] from [http://www.7-cpu.com/ 7-Zip LZMA Benchmark]
* [https://en.wikipedia.org/wiki/Phenom_%28processor%29 Phenom] triple-core, quad-core
* [https://en.wikipedia.org/wiki/Bobcat_%28microarchitecture%29 Bobcat (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Bulldozer_%28microarchitecture%29 Bulldozer (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29 Piledriver (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Steamroller_%28microarchitecture%29 Steamroller (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Excavator_%28microarchitecture%29 Excavator (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Zen_(microarchitecture) Zen (microarchitecture) from Wikipedia]
==Intel==
* [https://en.wikipedia.org/wiki/X86-64#Intel_64 EMT64 from Wikipedia]
* [https://en.wikipedia.org/wiki/Tick-Tock_model Tick-Tock model from Wikipedia]
* [https://en.wikipedia.org/wiki/Intel_Core_%28microarchitecture%29 Intel Core (microarchitecture from Wikipedia]
* <span id="Atom"></span>[https://en.wikipedia.org/wiki/Intel_Atom Intel Atom from Wikipedia]
* [https://en.wikipedia.org/wiki/Nehalem_%28microarchitecture%29 Nehalem (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Sandy_Bridge_%28microarchitecture%29 Sandy Bridge (microarchitecture) from Wikipedia]
* [http://www.7-cpu.com/cpu/SandyBridge.html Intel Sandy Bridge] from [http://www.7-cpu.com/ 7-Zip LZMA Benchmark]
* [https://en.wikipedia.org/wiki/Ivy_Bridge_%28microarchitecture%29 Ivy Bridge (microarchitecture) from Wikipedia]
* [http://www.7-cpu.com/cpu/IvyBridge.html Intel Ivy Bridge] from [http://www.7-cpu.com/ 7-Zip LZMA Benchmark]
* [https://en.wikipedia.org/wiki/Haswell_%28microarchitecture%29 Haswell (microarchitecture) from Wikipedia]
* [http://www.7-cpu.com/cpu/Haswell.html Intel Haswell] from [http://www.7-cpu.com/ 7-Zip LZMA Benchmark]
* [http://www.realworldtech.com/haswell-cpu/ Intel's Haswell CPU Microarchitecture] by [http://www.realworldtech.com/author/dkanter/ David Kanter], November 13, 2012
* [https://en.wikipedia.org/wiki/Broadwell_%28microarchitecture%29 Broadwell (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Skylake_%28microarchitecture%29 Skylake (microarchitecture) from Wikipedia]
* [https://en.wikipedia.org/wiki/Kaby_Lake Kaby Lake from Wikipedia]
* [https://en.wikipedia.org/wiki/Xeon_Phi Xeon Phi from Wikipedia]
==Instruction Sets==
* [https://en.wikipedia.org/wiki/X87 x87 from Wikipedia]
* [https://en.wikipedia.org/wiki/MMX_%28instruction_set%29 MMX from Wikipedia]
* [https://en.wikipedia.org/wiki/3DNow 3DNow! from Wikipedia]
* [https://en.wikipedia.org/wiki/Streaming_SIMD_Extensions Streaming SIMD Extensions from Wikipedia]
* [https://en.wikipedia.org/wiki/SSE2 SSE2 from Wikipedia] » [[SSE2]]
* [https://en.wikipedia.org/wiki/SSE3 SSE3 from Wikipedia] » [[SSE3]]
* [https://en.wikipedia.org/wiki/SSSE3 SSSE3 from Wikipedia] » [[SSSE3]]
* [https://en.wikipedia.org/wiki/SSE4 SSE4 from Wikipedia] » [[SSE4]]
* [http://de.wikipedia.org/wiki/SSE4a SSE4a from Wikipedia]
* [https://en.wikipedia.org/wiki/SSE5 SSE5 from Wikipedia] » [[SSE5]]
* [https://en.wikipedia.org/wiki/XOP_instruction_set XOP instruction set from Wikipedia] » [[XOP]]
* [https://en.wikipedia.org/wiki/Advanced_Vector_Extensions Advanced Vector Extensions (AVX) from Wikipedia] » [[AVX]]
: [https://en.wikipedia.org/wiki/AVX-512 AVX-512 from Wikipedia] » [[AVX-512]]
* [https://en.wikipedia.org/wiki/Transactional_Synchronization_Extensions Transactional Synchronization Extensions (TSX) from Wikipedia] ([https://en.wikipedia.org/wiki/Haswell_%28microarchitecture%29 Haswell])
* [http://software.intel.com/sites/landingpage/IntrinsicsGuide/ Intel Intrinsics Guide]
==Security Vulnerability==
* [https://en.wikipedia.org/wiki/Meltdown_(security_vulnerability) Meltdown (security vulnerability) from Wikipedia]
* [https://en.wikipedia.org/wiki/Spectre_(security_vulnerability) Spectre (security vulnerability) from Wikipedia]
* [https://googleprojectzero.blogspot.de/2018/01/reading-privileged-memory-with-side.html Project Zero: Reading privileged memory with a side-channel] by [https://thejh.net/ Jann Horn], [https://en.wikipedia.org/wiki/Project_Zero Project Zero], January 03, 2018
=References=
<references />
'''[[Hardware|Up one Level]]'''
