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<span id="PEXTPDEPProposal"></span>
=Early PEXT/PDEP Proposal=
In late 2006, [[Michael Sherwin]] already proposed a '''PEXTPDEP''' instruction, [[#PEXT|Parallel Bits Extract]] controlled by a source mask followed by [[#PDEP|Parallel Bits Deposit]] controlled by a destination mask <ref>[http://www.open-aurec.com/wbforum/viewtopic.php?f=4&t=5962 New instruction that intel/amd should add] by [[Michael Sherwin]], [[Computer Chess Forums|Winboard Forum]], December 05, 2006</ref> <ref>[http://www.talkchess.com/forum3/viewtopic.php?f=2&t=75333&start=8 Re: New AMD Zen 3 and Ryzen processors] by [[Michael Sherwin|Mike Sherwin]], [[CCC]], October 11, 2020</ref>.
However, it is not known whether his proposal was recognized by Intel engineers and had any influence on the design of the BMI2 PEXT and PDEP instructions.
