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Created page with "'''Home * Hardware * PowerPC''' FILE:Motorola PowerPC 603 die.JPG|border|right|thumb|Die shot of PowerPC 603 <ref>[https://en.wikipedia.org/wiki/Die_%28in..."
'''[[Main Page|Home]] * [[Hardware]] * PowerPC'''
[[FILE:Motorola PowerPC 603 die.JPG|border|right|thumb|Die shot of PowerPC 603 <ref>[https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 Die] shot of [[Motorola]] [https://en.wikipedia.org/wiki/PowerPC_600#PowerPC_603 PowerPC 603] microprocessor (XPC603FE75-2B), by [https://commons.wikimedia.org/wiki/User:Birdman86 Pauli Rautakorpi], April 29 2014, [https://creativecommons.org/licenses/by/3.0/deed.en CC BY 3.0], [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons]</ref> ]]
'''PowerPC''', (Power (Performance optimization with enhanced RISC) Performance Computing)<br/>
a [https://en.wikipedia.org/wiki/Reduced_instruction_set_computing RISC] [https://en.wikipedia.org/wiki/Computer_architecture architecture] and [https://en.wikipedia.org/wiki/Instruction_set ISA] created by the 1991 [[Apple]]–[[IBM]]–[[Motorola]] alliance dubbed [https://en.wikipedia.org/wiki/AIM_alliance AIM], well known for being used by Apple's [[Macintosh|Power Macintosh]] lines from 1994 to 2006, IBM [https://en.wikipedia.org/wiki/Supercomputer supercomputers], [https://en.wikipedia.org/wiki/IBM_eServer servers] and [https://en.wikipedia.org/wiki/Workstation workstations] i.e. [https://en.wikipedia.org/wiki/RS/6000 RS/6000], [https://en.wikipedia.org/wiki/Pegasos Pegasos], various [https://en.wikipedia.org/wiki/Home_video_game_console Game consoles] such as [https://en.wikipedia.org/wiki/Xbox_360 Xbox 360], [https://en.wikipedia.org/wiki/Wii Wii], still used inside the [[Amiga|AmigaOne]] and [https://en.wikipedia.org/wiki/AmigaOS_4 AmigaOS 4] PCs and [https://en.wikipedia.org/wiki/Embedded_system embedded systems].
=Architecture=
Derived from the 1990 [https://en.wikipedia.org/wiki/IBM_POWER_Instruction_Set_Architecture IBM POWER ISA] with its [https://en.wikipedia.org/wiki/POWER1 POWER1] and [https://en.wikipedia.org/wiki/POWER2 POWER2] processors, the PowerPC architecture added 64-bit specification that is backward compatible with the 32-bit mode <ref>[https://www.ibm.com/developerworks/library/l-ppc/ IBM PowerPC assembly]</ref>, and support for both [[Big-endian|big-endian]] and [[Little-endian|little-endian]] operation modes. 32-bit code will run natively unmodified on a 64-bit chip <ref>[http://www.csd.uwo.ca/~mburrel/stuff/ppc-asm.html PowerPC Assembly tutorial]</ref>. In the late 90s, PowerPC was extended by the 64-bit only '''PowerPC-AS''' ISA, and with advent of IBM's [https://en.wikipedia.org/wiki/POWER4 POWER4], PowerPC subsequently incorporated into the broader ISA superset and registered trademark governed by [https://en.wikipedia.org/wiki/Power.org Power.org], the [https://en.wikipedia.org/wiki/Power_Architecture Power Architecture] and POWER ISA. PowerPC CPUs have 32 general purpose registers, each either 32 bits or 64 bits in size depending on the chip, labelled r0 through r31. Integer instructions include [[BitScan#LeadingZeroCount|Count Leading Zeros]] <ref>[https://www.stmintz.com/ccc/index.php?id=425020 A data point for PowerPC bitboard program authors] by [[Steven Edwards]], [[CCC]], May 09, 2005</ref>, starting at the most significant bit with number 0 aka big-endian bit emumeration <ref>[https://www.ibm.com/support/knowledgecenter/ssw_aix_61/com.ibm.aix.alangref/idalangref_cntlzd_inst.htm IBM Knowledge Center - cntlzd (Count Leading Zeros Double Word) instruction]</ref>.
=Generations=
==G1 and G2==
'''PowerPC 600''' was the first generation of PowerPC, launching the PowerPC 601 in 1993 followed by the second generation PowerPC '''603''', PowerPC '''604''' and the first 64-bit PowerPC '''620'''. The 620 features a five stage [https://en.wikipedia.org/wiki/Instruction_pipelining instruction pipeline] - four instructions issued per clock, instruction dispatch in order, [https://en.wikipedia.org/wiki/Out-of-order_execution out-of-order execution], in-order completion - [https://en.wikipedia.org/wiki/Branch_predictor branch prediction] with [https://en.wikipedia.org/wiki/Speculative_execution speculative execution], 32k data and 32k instruction [[Memory|cache]] - 8 set associative, physically addressed - and [https://en.wikipedia.org/wiki/Multiprocessing multiprocessor] support with [https://en.wikipedia.org/wiki/Bus_sniffing bus snooping] for [https://en.wikipedia.org/wiki/Cache_coherence cache coherency] ([https://en.wikipedia.org/wiki/MESI_protocol MESI]). The 620 supports [https://en.wikipedia.org/wiki/Linearizability atomic operations] ([https://en.wikipedia.org/wiki/Read-modify-write read/modify/write]) with a pair of instructions, Load Word and Reserve (LWARX) and Store Conditional (STCX) <ref>[http://ra.ziti.uni-heidelberg.de/pages/lectures/fss10/ra/ext_info/powerpc620.pdf PowerPC 620 - Vorlesung Rechnerarchitektur, Heidelberg University] (pdf)</ref> <ref>[http://stackoverflow.com/questions/1147904/x86-equivalent-for-lwarx-and-stwcx x86 equivalent for LWARX and STWCX] - [https://en.wikipedia.org/wiki/Stack_Overflow Stack Overflow]</ref>.
<span id="G3"></span>
==G3 and G4==
Subsequent PowerPC designs were named and labeled by their apparent technology generation. That began with the '''G3''' which was an internal project name inside AIM for the development of what would become the 32-bit [https://en.wikipedia.org/wiki/PowerPC_7xx PowerPC 750 family] <ref>[https://en.wikipedia.org/wiki/PowerPC PowerPC from Wikipedia]</ref>. <span id="G4"></span>The fourth generation 32-bit [https://en.wikipedia.org/wiki/PowerPC_G4 PowerPC G4] (PowerPC 7400) debuted in August 1999 <ref>[https://en.wikipedia.org/wiki/PowerPC_G4 PowerPC G4 from Wikipedia]</ref>, and introduced [[AltiVec]] [[SIMD and SWAR Techniques|SIMD]] .
<span id="G5"></span>
==G5==
The 64-bit '''PowerPC G5''' (Apple) aka [https://en.wikipedia.org/wiki/PowerPC_970 PowerPC 970] was introduced in 2002. The PowerPC 970 is a single core derivative of the dual [https://en.wikipedia.org/wiki/POWER4 POWER4]. It has a hardware [https://en.wikipedia.org/wiki/Instruction_prefetch prefetch unit] and a three way [https://en.wikipedia.org/wiki/Branch_predictor branch prediction unit], eight execution units: two [[Combinatorial Logic#ALU|ALUs]], two double precision floating-point units, two load/store units and two [[AltiVec]] [[SIMD and SWAR Techniques|SIMD]] units.
=Chess Programs=
at times or exclusively dedicated to PowerPC
* [[Arthur]]
* [[Crafty]] <ref>[https://www.stmintz.com/ccc/index.php?id=425035 Re: A data point for PowerPC bitboard program authors] by [[Robert Hyatt]], [[CCC]], May 09, 2005</ref>
* [[Deep Blue]] ([https://en.wikipedia.org/wiki/RS/6000 RS/6000]) <ref>The way that the PowerPC chips inside Deep Blue work in parallel to break down and solve a chess-board problem is a pretty good analog for the way many scientists, working independently, advance our total understanding of the universe, or genetics..., from [https://www.research.ibm.com/deepblue/meet/html/d.3.3a.shtml IBM Research | Deep Blue | Overview]</ref>
* [[Hiarcs|Hiarcs 11]] <ref>[http://www.talkchess.com/forum/viewtopic.php?t=12843 HIARCS 11.1 SP / MP Macintosh has arrived!] by rafowell, [[CCC]], April 03, 2007</ref>
* [[Innovation]]
* [[MacChess]]
* [[McTobber]]
* [[The Sniper]]
* [[Wii Chess]]
* [[Zugzwang (Program)|Zugzwang]]
=Operating Systems=
* [https://en.wikipedia.org/wiki/AmigaOS_4 AmigaOS 4 from Wikipedia]
* [[Linux]] <ref>[https://en.wikipedia.org/wiki/MkLinux MkLinux from Wikipedia]</ref>
* [[Mac OS]]
* [[Unix|UNIX (AIX)]]
* [https://en.wikipedia.org/wiki/WarpOS WarpOS from Wikipedia]
* [[Windows|Windows NT]]
=See also=
* [[AltiVec]]
* [[Macintosh]]
=Publications=
* [https://www.researchgate.net/researcher/2091670479_MC_Becker M.C. Becker], [https://www.researchgate.net/researcher/5596820_C_R_Moore C.R. Moore], et al. ('''1993'''). ''[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=289646&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D289646 The PowerPC 601 microprocessor]''. IEEE Micro '93
* [https://www.researchgate.net/researcher/2091860528_MS_Allen M.S. Allen], [https://www.researchgate.net/researcher/2091670479_MC_Becker M.C. Becker] ('''1993'''). ''[[Multiprocessing aspects of the PowerPC 601]]''. [[IEEE]] [https://www.computer.org/csdl/proceedings/cmpcon/index.html CMPCON 1993]
* [http://dl.acm.org/author_page.cfm?id=81100336743&coll=DL&dl=ACM&trk=0&cfid=625619328&cftoken=18837961 Trung A. Diep], [http://dl.acm.org/author_page.cfm?id=81314484981&coll=DL&dl=ACM&trk=0&cfid=625619328&cftoken=18837961 Christopher Nelson], [http://dl.acm.org/author_page.cfm?id=81451600279&coll=DL&dl=ACM&trk=0&cfid=625619328&cftoken=18837961 John Paul Shen] ('''1994'''). ''[http://dl.acm.org/author_page.cfm?id=81100336743&coll=DL&dl=ACM&trk=0&cfid=625619328&cftoken=18837961 Performance Evaluation of the PowerPC 620 Microarchitecture]''. [[Carnegie Mellon University]], [https://www.ece.cmu.edu/research/publications/1994/CMU-ECE-1994-005.pdf pdf]
* [https://www.researchgate.net/profile/D_Levitan/publications D. Levitan], T. Thomas, P. Tu ('''1995'''). ''The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor''. [[IEEE]] COMPCON '95
* [https://www.linkedin.com/in/michael-koerner-76027a4 Michael Koerner], [https://www.linkedin.com/in/chakmingfai Ming Fai Chak], [https://www.linkedin.com/in/joe-ruthven-7ba4204 Joe Ruthven] ('''1995'''). ''PowerPC - An Inside View''. [[IBM]], [http://www.ibmfiles.com/ibmfiles/powerpc/itso_powerpc_inside_view.pdf pdf]
=Forum Posts=
* [https://www.stmintz.com/ccc/index.php?id=71754 G4 & AltiVec] by [[Will Singleton]], [[CCC]], October 04, 1999 » [[AltiVec]]
* [https://www.stmintz.com/ccc/index.php?id=78070 Mac G4 versus Pentium III] by Mark Andreoli, [[CCC]], November 16, 1999 » [[x86]]
* [https://www.stmintz.com/ccc/index.php?id=106960 PowerPC BitCounting Functions Speed] by [[William Bryant]], [[CCC]], April 20, 2000 » [[Population Count]]
* [https://www.stmintz.com/ccc/index.php?id=192267 powerpc 4 @ 1.3ghz] by Rajen Gupta, [[CCC]], October 07, 2001
* [https://www.stmintz.com/ccc/index.php?id=312343 An efficiency comparison data point for x86 vs PowerPC] by [[Steven Edwards]], [[CCC]], August 22, 2003
* [https://www.stmintz.com/ccc/index.php?id=425020 A data point for PowerPC bitboard program authors] by [[Steven Edwards]], [[CCC]], May 09, 2005 » [[BitScan]]
=External Links=
==Architectures==
* [https://en.wikipedia.org/wiki/PowerPC PowerPC from Wikipedia]
* [http://www.ibm.com/developerworks/systems/library/es-archguide-v2.html PowerPC Architecture Book, Version 2.02] (IBM)
* [https://en.wikipedia.org/wiki/IBM_POWER_Instruction_Set_Architecture IBM POWER Instruction Set Architecture | Wikipedia]
* [https://en.wikipedia.org/wiki/Power_Architecture Power Architecture from Wikipedia]
==Processors==
* [https://en.wikipedia.org/wiki/IBM_POWER_microprocessors IBM POWER microprocessors from Wikipedia]
===32-bit===
* [https://en.wikipedia.org/wiki/PowerPC_600 PowerPC 600 from Wikipedia]
* [https://en.wikipedia.org/wiki/PowerPC_7xx PowerPC 7xx from Wikipedia] (PowerPC G3)
* [https://en.wikipedia.org/wiki/Gekko_%28microprocessor%29 Gekko (microprocessor) from Wikipedia]
* [https://en.wikipedia.org/wiki/Broadway_%28microprocessor%29 Broadway (microprocessor) from Wikipedia]
* [https://en.wikipedia.org/wiki/MPC5xx MPC5xx from Wikipedia]
* [https://en.wikipedia.org/wiki/PowerPC_G4 PowerPC G4 from Wikipedia]
* [https://en.wikipedia.org/wiki/PowerPC_400 PowerPC 400 from Wikipedia]
* [https://en.wikipedia.org/wiki/PowerPC_e200 PowerPC e200 from Wikipedia]
===64-bit===
* [https://en.wikipedia.org/wiki/PowerPC_600#PowerPC_620 PowerPC 620 from Wikipedia]
* [https://en.wikipedia.org/wiki/POWER3 POWER3 from Wikipedia]
* [https://en.wikipedia.org/wiki/PowerPC_970 PowerPC 970 from Wikipedia] (PowerPC G5)
* [http://arstechnica.com/features/2002/10/ppc970/ Inside the IBM PowerPC 970 | Part I: Design Philosophy and Front End] by [http://arstechnica.com/author/hannibal/ Jon Stokes], [https://en.wikipedia.org/wiki/Ars_Technica Ars Technica], October 29, 2002
* [http://archive.arstechnica.com/cpu/03q1/ppc970/ppc970-0.html Inside the IBM PowerPC 970 | Part II: The Execution Core] by [http://arstechnica.com/author/hannibal/ Jon Stokes], [https://en.wikipedia.org/wiki/Ars_Technica Ars Technica]
* [https://en.wikipedia.org/wiki/POWER4 POWER4 from Wikipedia]
* [https://en.wikipedia.org/wiki/POWER5 POWER5 from Wikipedia]
* [https://en.wikipedia.org/wiki/Xenon_%28processor%29 Xenon (processor) from Wikipedia]
==Assembly==
* [http://www.ds.ewi.tudelft.nl/vakken/in1006/instruction-set/ Simplified PowerPC Instruction Set]
* [https://www.ibm.com/developerworks/library/l-ppc/ IBM PowerPC assembly]
* [http://www.csd.uwo.ca/~mburrel/stuff/ppc-asm.html PowerPC Assembly tutorial]
==Calling Conventions==
* [https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/LowLevelABI/100-32-bit_PowerPC_Function_Calling_Conventions/32bitPowerPC.html#//apple_ref/doc/uid/TP40002438-SW20 32-bit PowerPC Function Calling Conventions] (Apple)
* [https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html 64-bit PowerPC Function Calling Conventions] (Apple)
==MISC==
* [https://en.wikipedia.org/wiki/Macintosh_Programmer%27s_Workshop Macintosh Programmer's Workshop from Wikipedia] » [[Macintosh]]
* [https://en.wikipedia.org/wiki/Universal_binary Universal binary from Wikipedia] » [[x86]], [[x86-64]]
=References=
<references />
'''[[Hardware|Up one Level]]'''
[[Category:Die]]
[[FILE:Motorola PowerPC 603 die.JPG|border|right|thumb|Die shot of PowerPC 603 <ref>[https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 Die] shot of [[Motorola]] [https://en.wikipedia.org/wiki/PowerPC_600#PowerPC_603 PowerPC 603] microprocessor (XPC603FE75-2B), by [https://commons.wikimedia.org/wiki/User:Birdman86 Pauli Rautakorpi], April 29 2014, [https://creativecommons.org/licenses/by/3.0/deed.en CC BY 3.0], [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons]</ref> ]]
'''PowerPC''', (Power (Performance optimization with enhanced RISC) Performance Computing)<br/>
a [https://en.wikipedia.org/wiki/Reduced_instruction_set_computing RISC] [https://en.wikipedia.org/wiki/Computer_architecture architecture] and [https://en.wikipedia.org/wiki/Instruction_set ISA] created by the 1991 [[Apple]]–[[IBM]]–[[Motorola]] alliance dubbed [https://en.wikipedia.org/wiki/AIM_alliance AIM], well known for being used by Apple's [[Macintosh|Power Macintosh]] lines from 1994 to 2006, IBM [https://en.wikipedia.org/wiki/Supercomputer supercomputers], [https://en.wikipedia.org/wiki/IBM_eServer servers] and [https://en.wikipedia.org/wiki/Workstation workstations] i.e. [https://en.wikipedia.org/wiki/RS/6000 RS/6000], [https://en.wikipedia.org/wiki/Pegasos Pegasos], various [https://en.wikipedia.org/wiki/Home_video_game_console Game consoles] such as [https://en.wikipedia.org/wiki/Xbox_360 Xbox 360], [https://en.wikipedia.org/wiki/Wii Wii], still used inside the [[Amiga|AmigaOne]] and [https://en.wikipedia.org/wiki/AmigaOS_4 AmigaOS 4] PCs and [https://en.wikipedia.org/wiki/Embedded_system embedded systems].
=Architecture=
Derived from the 1990 [https://en.wikipedia.org/wiki/IBM_POWER_Instruction_Set_Architecture IBM POWER ISA] with its [https://en.wikipedia.org/wiki/POWER1 POWER1] and [https://en.wikipedia.org/wiki/POWER2 POWER2] processors, the PowerPC architecture added 64-bit specification that is backward compatible with the 32-bit mode <ref>[https://www.ibm.com/developerworks/library/l-ppc/ IBM PowerPC assembly]</ref>, and support for both [[Big-endian|big-endian]] and [[Little-endian|little-endian]] operation modes. 32-bit code will run natively unmodified on a 64-bit chip <ref>[http://www.csd.uwo.ca/~mburrel/stuff/ppc-asm.html PowerPC Assembly tutorial]</ref>. In the late 90s, PowerPC was extended by the 64-bit only '''PowerPC-AS''' ISA, and with advent of IBM's [https://en.wikipedia.org/wiki/POWER4 POWER4], PowerPC subsequently incorporated into the broader ISA superset and registered trademark governed by [https://en.wikipedia.org/wiki/Power.org Power.org], the [https://en.wikipedia.org/wiki/Power_Architecture Power Architecture] and POWER ISA. PowerPC CPUs have 32 general purpose registers, each either 32 bits or 64 bits in size depending on the chip, labelled r0 through r31. Integer instructions include [[BitScan#LeadingZeroCount|Count Leading Zeros]] <ref>[https://www.stmintz.com/ccc/index.php?id=425020 A data point for PowerPC bitboard program authors] by [[Steven Edwards]], [[CCC]], May 09, 2005</ref>, starting at the most significant bit with number 0 aka big-endian bit emumeration <ref>[https://www.ibm.com/support/knowledgecenter/ssw_aix_61/com.ibm.aix.alangref/idalangref_cntlzd_inst.htm IBM Knowledge Center - cntlzd (Count Leading Zeros Double Word) instruction]</ref>.
=Generations=
==G1 and G2==
'''PowerPC 600''' was the first generation of PowerPC, launching the PowerPC 601 in 1993 followed by the second generation PowerPC '''603''', PowerPC '''604''' and the first 64-bit PowerPC '''620'''. The 620 features a five stage [https://en.wikipedia.org/wiki/Instruction_pipelining instruction pipeline] - four instructions issued per clock, instruction dispatch in order, [https://en.wikipedia.org/wiki/Out-of-order_execution out-of-order execution], in-order completion - [https://en.wikipedia.org/wiki/Branch_predictor branch prediction] with [https://en.wikipedia.org/wiki/Speculative_execution speculative execution], 32k data and 32k instruction [[Memory|cache]] - 8 set associative, physically addressed - and [https://en.wikipedia.org/wiki/Multiprocessing multiprocessor] support with [https://en.wikipedia.org/wiki/Bus_sniffing bus snooping] for [https://en.wikipedia.org/wiki/Cache_coherence cache coherency] ([https://en.wikipedia.org/wiki/MESI_protocol MESI]). The 620 supports [https://en.wikipedia.org/wiki/Linearizability atomic operations] ([https://en.wikipedia.org/wiki/Read-modify-write read/modify/write]) with a pair of instructions, Load Word and Reserve (LWARX) and Store Conditional (STCX) <ref>[http://ra.ziti.uni-heidelberg.de/pages/lectures/fss10/ra/ext_info/powerpc620.pdf PowerPC 620 - Vorlesung Rechnerarchitektur, Heidelberg University] (pdf)</ref> <ref>[http://stackoverflow.com/questions/1147904/x86-equivalent-for-lwarx-and-stwcx x86 equivalent for LWARX and STWCX] - [https://en.wikipedia.org/wiki/Stack_Overflow Stack Overflow]</ref>.
<span id="G3"></span>
==G3 and G4==
Subsequent PowerPC designs were named and labeled by their apparent technology generation. That began with the '''G3''' which was an internal project name inside AIM for the development of what would become the 32-bit [https://en.wikipedia.org/wiki/PowerPC_7xx PowerPC 750 family] <ref>[https://en.wikipedia.org/wiki/PowerPC PowerPC from Wikipedia]</ref>. <span id="G4"></span>The fourth generation 32-bit [https://en.wikipedia.org/wiki/PowerPC_G4 PowerPC G4] (PowerPC 7400) debuted in August 1999 <ref>[https://en.wikipedia.org/wiki/PowerPC_G4 PowerPC G4 from Wikipedia]</ref>, and introduced [[AltiVec]] [[SIMD and SWAR Techniques|SIMD]] .
<span id="G5"></span>
==G5==
The 64-bit '''PowerPC G5''' (Apple) aka [https://en.wikipedia.org/wiki/PowerPC_970 PowerPC 970] was introduced in 2002. The PowerPC 970 is a single core derivative of the dual [https://en.wikipedia.org/wiki/POWER4 POWER4]. It has a hardware [https://en.wikipedia.org/wiki/Instruction_prefetch prefetch unit] and a three way [https://en.wikipedia.org/wiki/Branch_predictor branch prediction unit], eight execution units: two [[Combinatorial Logic#ALU|ALUs]], two double precision floating-point units, two load/store units and two [[AltiVec]] [[SIMD and SWAR Techniques|SIMD]] units.
=Chess Programs=
at times or exclusively dedicated to PowerPC
* [[Arthur]]
* [[Crafty]] <ref>[https://www.stmintz.com/ccc/index.php?id=425035 Re: A data point for PowerPC bitboard program authors] by [[Robert Hyatt]], [[CCC]], May 09, 2005</ref>
* [[Deep Blue]] ([https://en.wikipedia.org/wiki/RS/6000 RS/6000]) <ref>The way that the PowerPC chips inside Deep Blue work in parallel to break down and solve a chess-board problem is a pretty good analog for the way many scientists, working independently, advance our total understanding of the universe, or genetics..., from [https://www.research.ibm.com/deepblue/meet/html/d.3.3a.shtml IBM Research | Deep Blue | Overview]</ref>
* [[Hiarcs|Hiarcs 11]] <ref>[http://www.talkchess.com/forum/viewtopic.php?t=12843 HIARCS 11.1 SP / MP Macintosh has arrived!] by rafowell, [[CCC]], April 03, 2007</ref>
* [[Innovation]]
* [[MacChess]]
* [[McTobber]]
* [[The Sniper]]
* [[Wii Chess]]
* [[Zugzwang (Program)|Zugzwang]]
=Operating Systems=
* [https://en.wikipedia.org/wiki/AmigaOS_4 AmigaOS 4 from Wikipedia]
* [[Linux]] <ref>[https://en.wikipedia.org/wiki/MkLinux MkLinux from Wikipedia]</ref>
* [[Mac OS]]
* [[Unix|UNIX (AIX)]]
* [https://en.wikipedia.org/wiki/WarpOS WarpOS from Wikipedia]
* [[Windows|Windows NT]]
=See also=
* [[AltiVec]]
* [[Macintosh]]
=Publications=
* [https://www.researchgate.net/researcher/2091670479_MC_Becker M.C. Becker], [https://www.researchgate.net/researcher/5596820_C_R_Moore C.R. Moore], et al. ('''1993'''). ''[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=289646&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D289646 The PowerPC 601 microprocessor]''. IEEE Micro '93
* [https://www.researchgate.net/researcher/2091860528_MS_Allen M.S. Allen], [https://www.researchgate.net/researcher/2091670479_MC_Becker M.C. Becker] ('''1993'''). ''[[Multiprocessing aspects of the PowerPC 601]]''. [[IEEE]] [https://www.computer.org/csdl/proceedings/cmpcon/index.html CMPCON 1993]
* [http://dl.acm.org/author_page.cfm?id=81100336743&coll=DL&dl=ACM&trk=0&cfid=625619328&cftoken=18837961 Trung A. Diep], [http://dl.acm.org/author_page.cfm?id=81314484981&coll=DL&dl=ACM&trk=0&cfid=625619328&cftoken=18837961 Christopher Nelson], [http://dl.acm.org/author_page.cfm?id=81451600279&coll=DL&dl=ACM&trk=0&cfid=625619328&cftoken=18837961 John Paul Shen] ('''1994'''). ''[http://dl.acm.org/author_page.cfm?id=81100336743&coll=DL&dl=ACM&trk=0&cfid=625619328&cftoken=18837961 Performance Evaluation of the PowerPC 620 Microarchitecture]''. [[Carnegie Mellon University]], [https://www.ece.cmu.edu/research/publications/1994/CMU-ECE-1994-005.pdf pdf]
* [https://www.researchgate.net/profile/D_Levitan/publications D. Levitan], T. Thomas, P. Tu ('''1995'''). ''The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor''. [[IEEE]] COMPCON '95
* [https://www.linkedin.com/in/michael-koerner-76027a4 Michael Koerner], [https://www.linkedin.com/in/chakmingfai Ming Fai Chak], [https://www.linkedin.com/in/joe-ruthven-7ba4204 Joe Ruthven] ('''1995'''). ''PowerPC - An Inside View''. [[IBM]], [http://www.ibmfiles.com/ibmfiles/powerpc/itso_powerpc_inside_view.pdf pdf]
=Forum Posts=
* [https://www.stmintz.com/ccc/index.php?id=71754 G4 & AltiVec] by [[Will Singleton]], [[CCC]], October 04, 1999 » [[AltiVec]]
* [https://www.stmintz.com/ccc/index.php?id=78070 Mac G4 versus Pentium III] by Mark Andreoli, [[CCC]], November 16, 1999 » [[x86]]
* [https://www.stmintz.com/ccc/index.php?id=106960 PowerPC BitCounting Functions Speed] by [[William Bryant]], [[CCC]], April 20, 2000 » [[Population Count]]
* [https://www.stmintz.com/ccc/index.php?id=192267 powerpc 4 @ 1.3ghz] by Rajen Gupta, [[CCC]], October 07, 2001
* [https://www.stmintz.com/ccc/index.php?id=312343 An efficiency comparison data point for x86 vs PowerPC] by [[Steven Edwards]], [[CCC]], August 22, 2003
* [https://www.stmintz.com/ccc/index.php?id=425020 A data point for PowerPC bitboard program authors] by [[Steven Edwards]], [[CCC]], May 09, 2005 » [[BitScan]]
=External Links=
==Architectures==
* [https://en.wikipedia.org/wiki/PowerPC PowerPC from Wikipedia]
* [http://www.ibm.com/developerworks/systems/library/es-archguide-v2.html PowerPC Architecture Book, Version 2.02] (IBM)
* [https://en.wikipedia.org/wiki/IBM_POWER_Instruction_Set_Architecture IBM POWER Instruction Set Architecture | Wikipedia]
* [https://en.wikipedia.org/wiki/Power_Architecture Power Architecture from Wikipedia]
==Processors==
* [https://en.wikipedia.org/wiki/IBM_POWER_microprocessors IBM POWER microprocessors from Wikipedia]
===32-bit===
* [https://en.wikipedia.org/wiki/PowerPC_600 PowerPC 600 from Wikipedia]
* [https://en.wikipedia.org/wiki/PowerPC_7xx PowerPC 7xx from Wikipedia] (PowerPC G3)
* [https://en.wikipedia.org/wiki/Gekko_%28microprocessor%29 Gekko (microprocessor) from Wikipedia]
* [https://en.wikipedia.org/wiki/Broadway_%28microprocessor%29 Broadway (microprocessor) from Wikipedia]
* [https://en.wikipedia.org/wiki/MPC5xx MPC5xx from Wikipedia]
* [https://en.wikipedia.org/wiki/PowerPC_G4 PowerPC G4 from Wikipedia]
* [https://en.wikipedia.org/wiki/PowerPC_400 PowerPC 400 from Wikipedia]
* [https://en.wikipedia.org/wiki/PowerPC_e200 PowerPC e200 from Wikipedia]
===64-bit===
* [https://en.wikipedia.org/wiki/PowerPC_600#PowerPC_620 PowerPC 620 from Wikipedia]
* [https://en.wikipedia.org/wiki/POWER3 POWER3 from Wikipedia]
* [https://en.wikipedia.org/wiki/PowerPC_970 PowerPC 970 from Wikipedia] (PowerPC G5)
* [http://arstechnica.com/features/2002/10/ppc970/ Inside the IBM PowerPC 970 | Part I: Design Philosophy and Front End] by [http://arstechnica.com/author/hannibal/ Jon Stokes], [https://en.wikipedia.org/wiki/Ars_Technica Ars Technica], October 29, 2002
* [http://archive.arstechnica.com/cpu/03q1/ppc970/ppc970-0.html Inside the IBM PowerPC 970 | Part II: The Execution Core] by [http://arstechnica.com/author/hannibal/ Jon Stokes], [https://en.wikipedia.org/wiki/Ars_Technica Ars Technica]
* [https://en.wikipedia.org/wiki/POWER4 POWER4 from Wikipedia]
* [https://en.wikipedia.org/wiki/POWER5 POWER5 from Wikipedia]
* [https://en.wikipedia.org/wiki/Xenon_%28processor%29 Xenon (processor) from Wikipedia]
==Assembly==
* [http://www.ds.ewi.tudelft.nl/vakken/in1006/instruction-set/ Simplified PowerPC Instruction Set]
* [https://www.ibm.com/developerworks/library/l-ppc/ IBM PowerPC assembly]
* [http://www.csd.uwo.ca/~mburrel/stuff/ppc-asm.html PowerPC Assembly tutorial]
==Calling Conventions==
* [https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/LowLevelABI/100-32-bit_PowerPC_Function_Calling_Conventions/32bitPowerPC.html#//apple_ref/doc/uid/TP40002438-SW20 32-bit PowerPC Function Calling Conventions] (Apple)
* [https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html 64-bit PowerPC Function Calling Conventions] (Apple)
==MISC==
* [https://en.wikipedia.org/wiki/Macintosh_Programmer%27s_Workshop Macintosh Programmer's Workshop from Wikipedia] » [[Macintosh]]
* [https://en.wikipedia.org/wiki/Universal_binary Universal binary from Wikipedia] » [[x86]], [[x86-64]]
=References=
<references />
'''[[Hardware|Up one Level]]'''
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