25,161
edits
Changes
Created page with "'''Home * Hardware * Memory''' [[FILE:RNA-comparedto-DNA thymineAndUracilCorrected.png|border|right|thumb|[https://en.wikipedia.org/wiki/RNA RNA], biologica..."
'''[[Main Page|Home]] * [[Hardware]] * Memory'''
[[FILE:RNA-comparedto-DNA thymineAndUracilCorrected.png|border|right|thumb|[https://en.wikipedia.org/wiki/RNA RNA], biological [https://en.wikipedia.org/wiki/Data_storage_device data storage] <ref>[https://en.wikipedia.org/wiki/Data_storage_device Data storage device from Wikipedia]</ref> ]]
'''Memory''' is the ability to [https://en.wikipedia.org/wiki/Store store], retain, and [https://en.wikipedia.org/wiki/Recall_%28memory%29 recall] [https://en.wikipedia.org/wiki/Information information] and [https://en.wikipedia.org/wiki/Experience experiences] as researched in [[Cognition|cognitive science]]. Computer memory refers to [https://en.wikipedia.org/wiki/Peripheral physical devices] used to store [[Data|data]] and sequences of instructions ([[Program|programs]]) on a temporary or permanent basis, typically distinguished as fast [https://en.wikipedia.org/wiki/Random_access_memory random-access memory] and relatively slow [https://en.wikipedia.org/wiki/Computer_data_storage data storage].
<span id="FlipFlop"></span>
=Flip-Flop=
A [https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29 flip-flop] or [https://en.wikipedia.org/wiki/Latch_%28electronics%29 latch] is a one [[Bit|bit]] memory. For instance a simple [https://en.wikipedia.org/wiki/Relay relay] (K1) with its contact parallel to the On-push-button S2, "remembers" whether last action was pushing S1 (reset) or S2 (set) <ref>[http://de.wikipedia.org/wiki/Selbsthaltefunktion Selbsthaltefunktion from Wikidepia.de] (German)</ref> .
[[FILE:Selbsthaltung.gif|none|border|text-bottom]]
A [https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#RS_.28Reset-Set.29_flip-flop RS flip-flop] is a pair of cross-coupled [[Combinatorial Logic#NAND|NAND]] or [[Combinatorial Logic#NOR|NOR-gates]], where the outputs are feed back to the inputs. A [https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#D_.28Delay.29_flip-flop D flip-flop], the most common flip-flop, stores the input D with the rising edge (0-1 transition) of a clock.
{| class="wikitable"
|-
! RS flip-flop
! D flip-flop
! Discrete
|-
| [[FILE:RS flipflop.svg|none|border|text-bottom|220px]]
| [[FILE:D-Type Flip-flop.svg|none|border|text-bottom|180px]]
| rowspan="2=" | [[FILE:flipflop6as.jpg|none|border|text-bottom|260px|link=http://ljkrakauer.com/LJK/essays/bits.htm]]
|-
| [[FILE:R-S mk2.gif|none|border|text-bottom|220px]]
| [[FILE:Edge triggered D flip flop.svg|none|border|text-bottom|180px]]
|-
| from two NOR (red == 1) <ref>[https://en.wikipedia.org/wiki/Latch_%28electronics%29 Latch (electronics) from Wikipedia]</ref>
| from six NAND <ref>[https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29 Flip-flop (electronics) from Wikipedia]</ref>
| [[PDP-6]] flip-flop <ref>[http://ljkrakauer.com/LJK/essays/bits.htm Bits] by [[Lawrence J. Krakauer]]</ref> <ref>[http://bitsavers.trailing-edge.com/pdf/dec/pdp6/F-67_circuitInstr_May66.pdf PDP-6 Circuit Instruction Manual, © 1966, Digital Equipment Corporation] (pdf)</ref>
|}
* [https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29 Flip-flop (electronics) from Wikipedia]
* [https://en.wikipedia.org/wiki/Latch_%28electronics%29 Latch (electronics) from Wikipedia]
<span id="Latches"></span>
=N-Bit Latches=
N-Bit latches are [[Array|arrays]] of one-bit latches or flip-flops typically as wide as a connected parallel [https://en.wikipedia.org/wiki/Bus_%28computing%29 data-bus]. They may be used as a [https://en.wikipedia.org/wiki/Processor_register registers] or [https://en.wikipedia.org/wiki/Scratchpad_RAM scratchpad RAM] inside a [https://en.wikipedia.org/wiki/CPU central processing unit].
<span id="RAM"></span>
=RAM=
[https://en.wikipedia.org/wiki/Random_access_memory Random access memory] is a fast form of computer memory and refers to the idea that any piece of [[Data|data]] can be stored and retrieved in a constant time, regardless of its physical location and whether or not it is related to the previous piece of data.
* [https://en.wikipedia.org/wiki/Random_access_memory Random-access memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Volatile_memory Volatile memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Phase-change_memory Phase-change memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Ferroelectric_RAM Ferroelectric RAM from Wikipedia]
<span id="StaticRAM"></span>
==Static RAM==
[https://en.wikipedia.org/wiki/Static_random_access_memory Static RAM] (SRAM) is an array of latches, where each latch has a unique [https://en.wikipedia.org/wiki/Memory_address address], which connects the addressed latch to its [https://en.wikipedia.org/wiki/Bus_%28computing%29 data-bus], often used as [https://en.wikipedia.org/wiki/Cache#CPU_cache CPU cache].
* [https://en.wikipedia.org/wiki/Static_random_access_memory Static random access memory from Wikipedia]
<span id="DynamicRAM"></span>
==Dynamic RAM==
[https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory] (DRAM) is a type of random access memory that stores each bit of data in a separate [https://en.wikipedia.org/wiki/Capacitor capacitor] within an electronic circuit. Since capacitors leak charge, the information eventually fades unless the capacitor charge is [https://en.wikipedia.org/wiki/Memory_refresh refreshed] periodically, which is the reason to call that memory dynamic. Since DRAM takes only one [https://en.wikipedia.org/wiki/Transistor transistor] and capacitor per bit, it is therefor used as cheap main memory part of recent [https://en.wikipedia.org/wiki/Computer_data_storage computer data storage], despite its worse latency compared to SRAM.
* [https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory from Wikipedia]
: [https://en.wikipedia.org/wiki/SDRAM Synchronous dynamic random access memory (SDRAM)]
: [https://en.wikipedia.org/wiki/DDR_SDRAM DDR SDRAM] with [https://en.wikipedia.org/wiki/Double_data_rate Double data rate]
* [https://en.wikipedia.org/wiki/Interleaved_memory Interleaved memory]
* [https://en.wikipedia.org/wiki/SDRAM_latency SDRAM latency]
* [https://en.wikipedia.org/wiki/CAS_latency CAS latency]
* [https://en.wikipedia.org/wiki/Memory_controller Memory controller]
* [https://en.wikipedia.org/wiki/Memory_geometry Memory geometry]
* [https://en.wikipedia.org/wiki/Hybrid_Memory_Cube Hybrid Memory Cube]
[[FILE:Square array of mosfet cells read.png|none|border|text-bottom|480px]]
DRAM write at a 4 by 4 array <ref>[https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory from Wikipedia]</ref>
<span id="ROM"></span>
=ROM=
[https://en.wikipedia.org/wiki/Read-only_memory Read-only memory] (ROM) is a class of storage programmed once and mainly used to distribute [https://en.wikipedia.org/wiki/Firmware firmware]. [https://en.wikipedia.org/wiki/EPROM EPROMs] have a small quartz window which admits UV light for erasure <ref>[http://www.6502.org/users/dallas/SYM/SYM%20Projects/2716-2532%20EPROM%20BURNER/2716-2532.htm How to program a 2716]</ref> . ROM or EPROM were often embedded inside a [https://en.wikipedia.org/wiki/Microcontroller microcontroller] in conjunction with some RAM. They were often used in [[Dedicated Chess Computers|dedicated chess computers]].
[[FILE:EPROMs National Semiconductor.jpg|none|border|480px]]
[https://en.wikipedia.org/wiki/National_Semiconductor National Semiconductor] [https://en.wikipedia.org/wiki/EPROM#EPROM_generations,_sizes_and_types EPROMs 2764 and 2716] <ref>[https://commons.wikimedia.org/wiki/Category:EPROM_2716 Category:EPROM 2716 - Wikimedia Commons]</ref>
Since each data-bit stored in a ROM is a boolean function of its inputs or address, a ROM is also used to implement [[Combinatorial Logic|combinatorial logic]].
* [https://en.wikipedia.org/wiki/Read-only_memory Read-only memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Non-volatile_memory Non-volatile memory from Wikipedia]
=Auxiliary Storage=
Beside the computer's random access main memory, [https://en.wikipedia.org/wiki/Computer_data_storage auxiliary storage] refer to [https://en.wikipedia.org/wiki/Mass_storage mass storage] like [https://en.wikipedia.org/wiki/Optical_disc optical discs], and [https://en.wikipedia.org/wiki/Magnetic_storage magnetic storage] [https://en.wikipedia.org/wiki/Hard_disk_drive hard disk drives]. Those devices are usually connected via a [https://en.wikipedia.org/wiki/Serial_communication serial] bus, and accessed via [https://en.wikipedia.org/wiki/Stream_%28computing%29 streams].
[[FILE:Intelligent_Chess_1_20x20.JPG|none|border|text-bottom|480px|link=http://www.chesscomputeruk.com/html/intelligent_chess.html]]
[https://en.wikipedia.org/wiki/Compact_Cassette Compact Cassette] as Auxiliary Storage in [[Intelligent Chess]] <ref>[http://www.chesscomputeruk.com/html/intelligent_chess.html Intelligent Chess] from [http://www.chesscomputeruk.com/index.html Chess Computer UK] by [[Mike Watters]]</ref>
* [https://en.wikipedia.org/wiki/Computer_data_storage Computer data storage from Wikipedia]
* [https://en.wikipedia.org/wiki/Computer_data_storage Auxiliary storage]
* [https://en.wikipedia.org/wiki/Mass_storage Mass storage]
* [https://en.wikipedia.org/wiki/Magnetic_storage Magnetic storage]
* [https://en.wikipedia.org/wiki/Magnetic_tape_data_storage Magnetic tape data storage]
* [https://en.wikipedia.org/wiki/Floppy_disk Floppy disk]
* [https://en.wikipedia.org/wiki/Hard_disk_drive Hard disk drive]
* [https://en.wikipedia.org/wiki/RAID RAID]
* [https://en.wikipedia.org/wiki/Optical_disc Optical discs]
* [https://en.wikipedia.org/wiki/Compact_Disc Compact Disc]
* [https://en.wikipedia.org/wiki/DVD DVD]
* [https://en.wikipedia.org/wiki/Blu-ray_Disc Blu-ray Disc]
* [https://en.wikipedia.org/wiki/Solid-state_drive Solid-state drive]
* <span id="Flash"></span>[https://en.wikipedia.org/wiki/Flash_memory Flash memory]
* [https://en.wikipedia.org/wiki/USB_flash_drive USB flash drive]
: <span id="USB3"></span>[https://en.wikipedia.org/wiki/USB_3.0 USB 3.0]
* [https://en.wikipedia.org/wiki/Memory_Stick Memory Stick]
* [https://en.wikipedia.org/wiki/Memory_card Memory card]
* [https://en.wikipedia.org/wiki/Secure_Digital Secure Digital (SD)]
* [https://en.wikipedia.org/wiki/Serial_ATA Serial ATA]
* [https://en.wikipedia.org/wiki/Parallel_ATA Parallel ATA]
* [https://en.wikipedia.org/wiki/3D_XPoint 3D XPoint from Wikipedia] <ref>[http://www.talkchess.com/forum/viewtopic.php?t=57149 3D XPoint] by [[Edmund Moshammer]], [[CCC]], August 02, 2015</ref>
=Historical Data Storage=
* [https://en.wikipedia.org/wiki/History_of_computing_hardware History of computing hardware from Wikipedia]
* [http://www.columbia.edu/acis/history/tubes.html Vacuum Tube Memory] from [http://www.columbia.edu/acis/history/index.html Columbia University Computing History]
* [https://en.wikipedia.org/wiki/Selectron_tube Selectron tube from Wikipedia]
* [https://en.wikipedia.org/wiki/Williams_tube Williams tube from Wikipedia]
* <span id="Core"></span>[https://en.wikipedia.org/wiki/Magnetic_core_memory Magnetic-core memory from Wikipedia]
: [[FILE:Coincident-current magnetic core.svg|none|border|text-bottom|320px]]
: <span id="Plated"></span>[https://en.wikipedia.org/wiki/Plated_wire_memory Plated wire memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Punched_card Punched card from Wikipedia]
* [https://en.wikipedia.org/wiki/Punched_tape Punched tape from Wikipedia]
* [https://en.wikipedia.org/wiki/Drum_memory Drum memory from Wikipedia]
: [[FILE:Pamiec bebnowa 1.jpg|none|border|text-bottom|320px]]
* [https://en.wikipedia.org/wiki/Delay_line_memory Delay line memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Magnetic_bubble_memory Bubble memory from Wikipedia]
=Memory Hierarchy=
* [https://en.wikipedia.org/wiki/Memory_hierarchy Memory hierarchy from Wikipedia]
: [[FILE:ComputerMemoryHierarchy.svg|none|border|text-bottom|640px|link=https://en.wikipedia.org/wiki/Memory_hierarchy]]
* [https://en.wikipedia.org/wiki/Memory_organisation Memory organisation from Wikipedia]
<span id="Management"></span>
=Memory Management=
Todays processors utilize all the above types of memory from small and fast to large but slow within the concepts of [https://en.wikipedia.org/wiki/Virtual_memory virtual memory], [https://en.wikipedia.org/wiki/Paging paging], [https://en.wikipedia.org/wiki/Memory_protection protection] and various [https://en.wikipedia.org/wiki/Cache caches].
* [https://en.wikipedia.org/wiki/Memory_management Memory management from Wikipedia]
* [https://en.wikipedia.org/wiki/Memory_management_unit Memory management unit from Wikipedia]
* [http://msdn.microsoft.com/en-us/library/aa366779%28v=VS.85%29.aspx MSDN - Memory Management] » [[Windows]]
* [http://www.memorymanagement.org/ The Memory Management Reference] [http://www.ravenbrook.com/ Ravenbrook]
* [https://en.wikipedia.org/wiki/Memory_protection Memory protection from Wikipedia]
<span id="Virtual"></span>
==Virtual Memory==
{|
|-
| [[FILE:Page table actions.svg|none|border|text-bottom|460px]]
| [[FILE:Virtual address space and physical address space relationship.svg|none|border|text-bottom|320px]]
|-
| [https://en.wikipedia.org/wiki/Physical_address Physical address] translation <ref>[https://en.wikipedia.org/wiki/Page_table Page table from Wikipedia]</ref>
| Virtual and physical address space <ref>[https://en.wikipedia.org/wiki/Virtual_address Virtual address from Wikipedia]</ref>
|}
* [https://en.wikipedia.org/wiki/Virtual_memory Virtual memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Memory_address Memory address from Wikipedia]
* [https://en.wikipedia.org/wiki/Physical_address Physical address from Wikipedia]
* [https://en.wikipedia.org/wiki/Virtual_address Virtual address from Wikipedia]
* [https://en.wikipedia.org/wiki/VAX Virtual Address eXtension (VAX) from Wikipedia]
<span id="Page"></span>
==Paging==
* [https://en.wikipedia.org/wiki/Page_%28computer_memory%29 Page (computer memory) from Wikipedia]
: [https://en.wikipedia.org/wiki/Page_table Page table]
: [https://en.wikipedia.org/wiki/Page_replacement_algorithm Page replacement algorithm]
: <span id="Paging"></span>[https://en.wikipedia.org/wiki/Paging Paging]
: [https://en.wikipedia.org/wiki/Demand_paging Demand Paging]
: [https://en.wikipedia.org/wiki/Page_fault Page fault]
: [https://en.wikipedia.org/wiki/Copy-on-write Copy-on-write]
<span id="TLB"></span>
==TLB==
* [https://en.wikipedia.org/wiki/Translation_Lookaside_Buffer Translation lookaside buffer (TLB)]
<span id="HugePages"></span>
==Huge Pages==
''Note that what [[Windows]] calls "large pages," [[Linux]] and [[Unix]] call "huge pages" or "huge TLB pages'' ([[x86]] and [[x86-64]])
* [https://en.wikipedia.org/wiki/Page_Size_Extension Page Size Extension from Wikipedia]
* [http://msdn.microsoft.com/en-us/library/aa366720%28v=vs.85%29.aspx MSDN - Large-Page Support] » [[Windows]]
* [http://lwn.net/Articles/374424/ Huge pages part 1 Introduction] by [http://www.csn.ul.ie/%7Emel/blog/index.php?/authors/1-Mel-Gorman Mel Gorman], [https://en.wikipedia.org/wiki/LWN.net LWN.net], February 16, 2010 » [[Linux]]
* [http://lwn.net/Articles/375096/ Huge pages part 2: Interfaces] by [http://www.csn.ul.ie/%7Emel/blog/index.php?/authors/1-Mel-Gorman Mel Gorman], [https://en.wikipedia.org/wiki/LWN.net LWN.net], February 24, 2010
* [http://lwn.net/Articles/376606/ Huge pages part 3: Administration] by [http://www.csn.ul.ie/%7Emel/blog/index.php?/authors/1-Mel-Gorman Mel Gorman], [https://en.wikipedia.org/wiki/LWN.net LWN.net], March 3, 2010
* [http://lwn.net/Articles/378641/ Huge pages part 4: benchmarking with huge pages] by [http://www.csn.ul.ie/%7Emel/blog/index.php?/authors/1-Mel-Gorman Mel Gorman], [https://en.wikipedia.org/wiki/LWN.net LWN.net], March 17, 2010
* [http://lwn.net/Articles/379748/ Huge pages part 5: A deeper look at TLBs and costs] by [http://www.csn.ul.ie/%7Emel/blog/index.php?/authors/1-Mel-Gorman Mel Gorman], [https://en.wikipedia.org/wiki/LWN.net LWN.net], March 23, 2010
* [http://lwn.net/Articles/423584/ Transparent huge pages in 2.6.38] by [http://kerneltrap.org/Jonathan_Corbet Jonathan Corbet], [https://en.wikipedia.org/wiki/LWN.net LWN.net], January 19, 2011
=Memory Model=
* [https://en.wikipedia.org/wiki/Memory_model_%28computing%29 Memory model (computing) from Wikipedia]
* [https://en.wikipedia.org/wiki/Consistency_model Consistency model from Wikipedia]
* [https://en.wikipedia.org/wiki/Memory_ordering Memory ordering from Wikipedia]
* [https://en.wikipedia.org/wiki/Memory_barrier Memory barrier from Wikipedia]
* [https://en.wikipedia.org/wiki/Flat_memory_model Flat memory model from Wikipedia]
* [https://en.wikipedia.org/wiki/Intel_Memory_Model Intel Memory Model from Wikipedia] » [[Intel]], [[x86]], [[C]], [[Cpp|C++]]
* [https://en.wikipedia.org/wiki/Java_Memory_Model Java Memory Model from Wikipedia] » [[Java]]
* [http://www.hpl.hp.com/personal/Hans_Boehm/c++mm/ Threads and memory model for C++] by [http://www.hpl.hp.com/personal/Hans_Boehm/ Hans J. Boehm]
* [http://golang.org/doc/go_mem.html The Go Memory Model] » [[Go (Programming Language)]]
<span id="Shared"></span>
==Shared Memory==
{{Shared Memory}}
==<span id="Cache"></span>Cache==
{{Cache}}
==Segmentation==
* [https://en.wikipedia.org/wiki/Memory_segmentation Memory segmentation from Wikipedia]
* [https://en.wikipedia.org/wiki/Data_segment Data segment]
* [https://en.wikipedia.org/wiki/.bss .bss]
* [https://en.wikipedia.org/wiki/Code_segment Code segment]
* [https://en.wikipedia.org/wiki/Segmentation_fault Segmentation fault]
* [https://en.wikipedia.org/wiki/SIGSEGV SIGSEGV]
* [https://en.wikipedia.org/wiki/X86_memory_segmentation x86 memory segmentation] » [[x86]]
* [http://software.intel.com/en-us/articles/memory-limits-applications-windows/ Memory Limits for Applications on Windows] by [http://software.intel.com/en-us/user/512685 Steve Lionel] ([[Intel]]), May 16, 2011» [[Windows]]
==Allocation==
* [https://en.wikipedia.org/wiki/Dynamic_memory_allocation Dynamic memory allocation from Wikipedia]
: [https://en.wikipedia.org/wiki/Manual_memory_management Manual memory management]
: [https://en.wikipedia.org/wiki/Memory_leak Memory leak]
: [https://en.wikipedia.org/wiki/Garbage_collection_%28computer_science%29 Garbage collection]
* [https://en.wikipedia.org/wiki/Stack-based_memory_allocation Stack-based memory allocation] » [[Stack]]
* [https://en.wikipedia.org/wiki/Buddy_memory_allocation Buddy memory allocation]
* [https://en.wikipedia.org/wiki/Hoard_memory_allocator Hoard memory allocator]
* [https://en.wikipedia.org/wiki/Memory_pool Memory pool]
<span id="Footprint"></span>
=Memory Footprint=
Beside their individual [https://en.wikipedia.org/wiki/Memory_footprint memory footprint], chess programs have to deal with huge memory areas of [[Transposition Table|transposition table]] and possibly caches for [[Endgame Tablebases|endgame table-]] or [[Endgame Bitbases|bitbases]] and their relative huge random access latencies.
* [https://en.wikipedia.org/wiki/Memory_footprint Memory footprint from Wikipedia]
* [http://www.freepatentsonline.com/y2007/0033371.html Method and apparatus for establishing a cache footprint for shared processor logical partitions]
* [https://en.wikipedia.org/wiki/Memory_timings Memory timings from Wikipedia]
* [https://en.wikipedia.org/wiki/Access_time Access time]
* [https://en.wikipedia.org/wiki/CAS_latency CAS latency]
* [https://en.wikipedia.org/wiki/Memory_bandwidth Memory bandwidth]
* [http://zsmith.co/bandwidth.html Bandwidth: a memory bandwidth benchmark for x86 / x86_64 based Linux/Windows/MacOSX] by Zack Smith
* [https://en.wikipedia.org/wiki/Cache_pollution Cache pollution]
* [https://en.wikipedia.org/wiki/Thrashing_%28computer_science%29 Thrashing (computer science)]
* [https://en.wikipedia.org/wiki/False_sharing False sharing from Wikipedia]
* [https://en.wikipedia.org/wiki/Miles_Davis_Quintet Miles Davis Quintet] - [https://en.wikipedia.org/wiki/Footprints_(composition) Footprints] ([[Videos#WayneShorter|Wayne Shorter]]), New York, 1966, [https://en.wikipedia.org/wiki/YouTube YouTube] Video
: [[Videos#MilesDavis|Miles Davis]], [[Videos#WayneShorter|Wayne Shorter]], [[Videos#HerbieHancock|Herbie Hancock]], [https://en.wikipedia.org/wiki/Ron_Carter Ron Carter], [https://en.wikipedia.org/wiki/Tony_Williams_(drummer) Tony Williams]
: {{#evu:https://www.youtube.com/watch?v=j7lkqxfvA78|alignment=left|valignment=top}}
* [http://krakowskascenamuzyczna.pl/tag/monika-malczak/ Monika Malczak Quartet] - [https://en.wikipedia.org/wiki/Footprints_(composition) Footprints], [http://www2.polskieradio.pl/studio/lutoslawski_en.aspx Witold Lutosławski Concert Studio of Polish Radio], [https://en.wikipedia.org/wiki/Warsaw Warsaw], May 20, 2016, [https://en.wikipedia.org/wiki/YouTube YouTube] Video
: [http://krakowskascenamuzyczna.pl/tag/monika-malczak/ Monika Malczak], [http://jazz.radionadzieja.pl/mateusz-gramburg-fortepian/ Mateusz Gramburg], [https://www.instagram.com/pure_o/ Paweł Zwierzyński-Pióro], [https://www.facebook.com/people/Micha%C5%82-Szeligowski/1505615273 Michał Szeligowski]
: {{#evu:https://www.youtube.com/watch?v=jpZ4B67xtII|alignment=left|valignment=top}}
=Multiprocessing=
* [[SMP]]
* [[NUMA]]
=Memory versus Search=
* [[Best-First]]
* [[Depth-First]]
* [[Endgame Tablebases]]
* [[Knowledge]]
* [[Learning]]
* [[MTD(f)]]
* [[Parallel Search]]
* [[Persistent Hash Table]]
* [[Space-Time Tradeoff]]
* [[SSS* and Dual*]]
* [[Transposition Table]]
=See also=
* [[Algorithms]]
* [[Array]]
* [[Cognition]]
* [[Combinatorial Logic]]
* [[Data]]
* [[Hash Table]]
* [[Psychology]]
* [[Queue]]
* [[Sequential Logic]]
* [[Shared Hash Table]]
* [[Stack]]
=Publications=
==Computer Memory==
===1960 ...===
* [https://en.wikipedia.org/wiki/Ken_Knowlton Kenneth C. Knowlton] ('''1965'''). ''A Fast storage allocator''. [[ACM#Communications|Communications of the ACM]], Vol. 8, No. 10 : 623-625
===1970 ...===
* [[Donald Eastlake]] ('''1977'''). ''[http://www.informatik.uni-trier.de/~ley/db/conf/vldb/Eastlake77.html Tertiary Memory Access and Performance in the Datacomputer]''. [http://www.informatik.uni-trier.de/~ley/db/conf/vldb/vldb77.html#Eastlake77 VLDB 1977]
===1980 ...===
* [[Ozalp Babaoglu]], [https://en.wikipedia.org/wiki/Bill_Joy William Joy] ('''1981'''). ''Converting a Swap-Based System to do Paging in an Architecture Lacking Page-Reference Bits''. Proceedings of the 8th SOSP, Operating Systems Review, Vol. 15, No. 5, pp. 78-86
* [[Bruce W. Leverett]], [http://genealogy.math.ndsu.nodak.edu/id.php?id=95738 Peter G. Hibbard] ('''1982'''). ''[http://onlinelibrary.wiley.com/doi/10.1002/spe.4380120606/abstract An Adaptive System for Dynamic Storage Allocation]''. [http://www.informatik.uni-trier.de/~ley/db/journals/spe/spe12.html#LeverettH82 Software: Practice and Experience], [http://onlinelibrary.wiley.com/doi/10.1002/spe.v12:6/issuetoc Vol. 12, No. 6], pp. 543-555
* [[Subir Bhattacharya]], [[Amitava Bagchi]] ('''1986'''). ''Making Best Use of Available Memory when Searching Game Trees.'' Proceedings of the 5th International Conference on Artificial Intelligence (AAAI-86), pp. 163-167. AAAI/MIT Press, Boston, MA.
===1990 ...===
* [[Peter W. Frey]] ('''1991'''). ''Memory-Based Expertise: Computer Chess vs. AI''. [[ICGA Journal#14_4|ICCA Journal, Vol. 14, No. 4]]
* [[Jos Uiterwijk]] ('''1992'''). ''Memory Efficiency in some Heuristics''. [[ICGA Journal#15_2|ICCA Journal, Vol. 15, No. 2]]
* [[Wim Pijls]], [[Arie de Bruin]] ('''1993'''). ''SSS*-like Algorithms in Constrained Memory.'' [[ICGA Journal#16_1|ICCA Journal, Vol. 16, No. 1]]
* [[Hermann Kaindl]], G. Kainz, A. Leeb, H. Smetana ('''1995'''). ''How to use limited memory in heuristic search''. Proceedings of the Fourteenth International Joint Conference on Artificial Intelligence (IJCAI-95), Montreal, Canada, pp. 236-242.
* [[Dennis Breuker]] ('''1998'''). ''Memory versus Search in Games''. Ph.D. thesis, [[Maastricht University]], pdf available via [http://www.dennisbreuker.nl/thesis/index.html Dennis Breuker's page]
* [[Harald Prokop]] ('''1999'''). ''Cache-Oblivious Algorithms''. Masters thesis, Department of Electrical Engineering and Computer Science, [[Massachusetts Institute of Technology|MIT]], [http://supertech.csail.mit.edu/papers/Prokop99.pdf pdf] <ref>[https://en.wikipedia.org/wiki/Cache-oblivious_algorithm Cache-oblivious algorithm from Wikipedia]</ref>
===2000 ...===
* [http://dblp.uni-trier.de/pers/hd/y/Yang:Yue Yue Yang], [http://dblp.uni-trier.de/pers/hd/g/Gopalakrishnan:Ganesh Ganesh Gopalakrishnan], [[Gary Lindstrom]] ('''2002'''). ''Specifying Java Thread Semantics Using a Uniform Memory Model''. [http://dblp.uni-trier.de/db/conf/java/java2002.html#YangGL02 Java Grande 2002], [http://formalverification.cs.utah.edu/yyang/papers/umm_old.pdf pdf]
* [[F. Warren Burton]], [http://dblp.uni-trier.de/pers/hd/s/Simpson:David_J= David J. Simpson] ('''2000'''). ''[http://www.sciencedirect.com/science/article/pii/S0167819100000533 Memory requirements for parallel programs]''. [http://www.journals.elsevier.com/parallel-computing/ Parallel Computing], Vol. 26, Nos. 13-14
* [[Mathematician#QWu|Qiang Wu]], [[Artem Petakov|Artem Pyatakov]], [[Mathematician#ASpiridonov|Alexey Spiridonov]], [http://liberty.princeton.edu/Publications/index.php?setselect=eraman Easwaran Raman], [[Mathematician#DWClark|Douglas W. Clark]], [[Mathematician#DIAugust|David I. August]] ('''2004'''). ''Exposing Memory Access Regularities Using Object-Relative Memory Profiling''. [http://dblp.uni-trier.de/db/conf/cgo/cgo2004.html#WuPSRCA04 CGO 2004], [http://www.cs.princeton.edu/~jqwu/orp_paper.pdf pdf]
* [http://de.wikipedia.org/wiki/Ulrich_Drepper Ulrich Drepper] ('''2007'''). ''What Every Programmer Should Know About Memory''. [http://www.akkadia.org/drepper/cpumemory.pdf pdf], also hosted by [https://en.wikipedia.org/wiki/LWN.net LWN.net]
: [http://lwn.net/Articles/250967/ Memory part 1]
: [http://lwn.net/Articles/252125/ Memory part 2: CPU caches]
: [http://lwn.net/Articles/253361/ Memory part 3: Virtual Memory]
: [http://lwn.net/Articles/254445/ Memory part 4: NUMA support]
: [http://lwn.net/Articles/255364/ Memory part 5: What programmers can do]
* [[David Silver]], [[Richard Sutton]], [[Martin Müller]] ('''2008'''). ''Sample-Based Learning and Search with Permanent and Transient Memories''. In Proceedings of the 25th International Conference on Machine Learning, [http://webdocs.cs.ualberta.ca/%7Esilver/David_Silver/Publications_files/dyna2.pdf pdf]
===2010 ...===
* [[Aaron Becker]], [http://charm.cs.uiuc.edu/people/gengbinzheng Gengbin Zheng], [[Mathematician#LaxKale|Laxmikant Kale]] ('''2011'''). ''Distributed Memory Load Balancing''. [http://www.springer.com/computer/swe/book/978-0-387-09765-7 Encyclopedia of Parallel Computing], [https://en.wikipedia.org/wiki/Springer_Science%2BBusiness_Media Springer]
* [https://en.wikipedia.org/wiki/George_Church George Church], [http://www.bme.jhu.edu/people/primary.php?id=1045 Yuan Gao], [http://openwetware.org/wiki/Sriram_Kosuri Sriram Kosuri] ('''2012'''). ''[http://www.sciencemag.org/content/early/2012/08/15/science.1226355 Next-Generation Digital Information Storage in DNA]''. [https://en.wikipedia.org/wiki/Science_%28journal%29 Science] <ref>[http://www.nature.com/news/dna-data-storage-breaks-records-1.11194 DNA data storage breaks records : Nature News & Comment] by [http://www.nature.com/stemcells/about_editor.html Monya Baker], August 16, 2012</ref> <ref>[http://www.talkchess.com/forum/viewtopic.php?t=44826 DNA data storage breaks records] by Terry McCracken, [[CCC]], August 18, 2012</ref>
==[[Cognition]]==
===1960 ...===
* [[Adriaan de Groot]] ('''1966'''). ''Perception and Memory versus Thought: Some Old Ideas and Recent Findings''. Problem Solving: Research, Method, and Theory (ed. B. Kleinmuntz), pp. 19-50. John Wiley, New York.
===1970 ...===
* [[Herbert Simon]], [[Kevin J. Gilmartin]] ('''1973'''). ''A Simulation of Memory for Chess Positions''. Cognitive Psychology, Vol. 5, pp. 29-46. [http://www.cs.wright.edu/~snarayan/isis/pdf/group5one.pdf pdf] » [[MAPP]]
* [[Peter W. Frey]], [[Peter Adesman]] ('''1976'''). ''[http://link.springer.com/article/10.3758%2FBF03213216?LI=true#page-1 Recall Memory for Visually Presented Chess Positions]''. [http://www.springer.com/psychology/cognitive+psychology/journal/13421 Memory & Cognition], Vol. 4, No. 5, 541-547
* [[Neil Charness]] ('''1976'''). ''[http://psycnet.apa.org/journals/xlm/2/6/641/ Memory for Chess Positions: Resistance to Interference]''. Journal of Experimental Psychology: Human Learning and Memory, Vol. 2, No. 6, pp. 641-653 » [[MAPP]]
* [[Judith Spencer Olson|Judith S. Reitman]] ('''1976'''). ''[http://deepblue.lib.umich.edu/handle/2027.42/33676 Mechanisms of Forgetting in Short-term Memory]''. [http://www.journals.elsevier.com/cognitive-psychology/ Cognitive Psychology], Vol. 2, No. 2
* [[Judith Spencer Olson|Judith S. Reitman]] ('''1976'''). ''[http://deepblue.lib.umich.edu/handle/2027.42/21741 Skilled Perception in Go: Deducing Memory Structures from Inter-Response Times]''. [http://www.journals.elsevier.com/cognitive-psychology/ Cognitive Psychology], Vol. 8, No, 3
* [[Sarah E. Goldin]] ('''1978'''). ''[http://psycnet.apa.org/journals/xlm/4/6/605/ Memory for the ordinary: Typicality effects in chess memory]''. Journal of Experimental Psychology: Human Learning and Memory, Vol. 4, No. 6, pp. 605-616
* [[Sarah E. Goldin]] ('''1979'''). ''[http://www.jstor.org/discover/10.2307/1421476?uid=3737864&uid=2129&uid=2&uid=70&uid=4&sid=21101400527007 Recognition memory for chess positions: Some preliminary research]''. [https://en.wikipedia.org/wiki/American_Journal_of_Psychology American Journal of Psychology], Vol 92, No. 1, pp. 19-32
===1980 ...===
* [[Marvin Minsky]] ('''1980'''). ''K-Lines: A Theory of Memory''. Cognitive Science 4, 117-133, [http://csjarchive.cogsci.rpi.edu/1980v04/i02/p0117p0133/MAIN.PDF pdf] <ref>[https://en.wikipedia.org/wiki/K-line_%28artificial_intelligence%29 K-line (artificial intelligence) from Wikipedia]</ref>
* [[Dennis H. Holding]], [[Robert I. Reynolds]] ('''1982'''). ''[http://link.springer.com/article/10.3758%2FBF03197635?LI=true#page-1 Recall or Evaluation of Chess Positions as Determinants of Chess Skill]''. [http://www.springer.com/psychology/cognitive+psychology/journal/13421 Memory & Cognition], Vol. 10, No. 3, 237-242
* [[A. Harry Klopf]] ('''1982'''). ''The Hedonistic Neuron: A Theory of Memory, Learning, and Intelligence''. Hemisphere Publishing Corporation, [[University of Michigan]]
===1990 ...===
* [[Fernand Gobet]] ('''1993'''). ''[http://people.brunel.ac.uk/%7Ehsstffg/papers/ModelChessMem/Chess%20Memory.html A Computer Model of Chess Memory].'' Proceedings of the 15th Annual Meeting of the Cognitive Science Society, pp. 463-468.
* [[Fernand Gobet]], [[Peter Jansen]] ('''1994'''). ''Towards a chess program based on a model of human memory.'' [[Advances in Computer Chess 7]]. [http://people.brunel.ac.uk/%7Ehsstffg/abstracts/chess_program.html abstract]
* [[Robert W. Howard]] ('''1995'''). ''Learning and Memory: Major Ideas, Principles, Issues and Applications''. Praeger, [http://www.amazon.com/Learning-Memory-Principles-Issues-Applications/dp/027594641X/ref=la_B001HPC7VM_1_1?ie=UTF8&qid=1352388827 amazon.com]
* [[Adriaan de Groot]], [[Fernand Gobet]] ('''1996'''). ''[http://people.brunel.ac.uk/%7Ehsstffg/abstracts/deGroot_abstract.html Perception and memory in chess]. Heuristics of the professional eye.'' Assen: Van Gorcum, The Netherlands. ISBN 90-232-2949-5. Chapter 9; A discussion: Two authors, two different views? [http://people.brunel.ac.uk/%7Ehsstffg/preprints/DeGroot_Gobet_Chapter_9.doc word reprint]
* [[Fernand Gobet]], [[Herbert Simon]] ('''1996'''). ''Templates in Chess Memory: A Mechanism for Recalling Several Boards.'' Cognitive Psychology, Vol. 31, pp. 1-40.
* [[Fernand Gobet]], [[Herbert Simon]] ('''1996'''). ''Recall of random and distorted positions: Implications for the theory of expertise.'' Memory & Cognition, 24, 493-503.
* [[Fernand Gobet]], [[Herbert Simon]] ('''1996'''). ''Recall of rapidly presented random chess positions is a function of skill.'' Psychonomic Bulletin & Review, 3, 159-163, [http://people.brunel.ac.uk/%7Ehsstffg/preprints/Recall_random_pos.doc word reprint]
* [[Fernand Gobet]], [[Herbert Simon]] ('''1998'''). ''Expert chess memory: Revisiting the chunking hypothesis.'' Memory, 6, 225-255
* [[Richard S. Schultetus]], [[Neil Charness]] ('''1999'''). ''Recall vs. position evaluation revisited: The importance of position-specific memory in chess skill''. [https://en.wikipedia.org/wiki/American_Journal_of_Psychology American Journal of Psychology], Vol. 112, No. 4, 555-569.
===2000 ...===
* [[Pertti Saariluoma]], [[Tei Laine]] ('''2001'''). ''[http://onlinelibrary.wiley.com/doi/10.1111/1467-9450.00223/abstract Novice construction of chess memory]''. [http://psychology.wikia.com/wiki/Scandinavian_Journal_of_Psychology Scandinavian Journal of Psychology], Vol. 42, No. 2 <ref>[[Fernand Gobet]] ('''2007'''). ''Chunk hierarchies and retrieval structures: Comments on Saariluoma and Laine. Scandinavian Journal of Psychology, 42''. [http://dspace.brunel.ac.uk/bitstream/2438/806/1/Saariluoma_Laine_reply.pdf pdf]</ref>
* [[Dharshan Kumaran]], [https://en.wikipedia.org/wiki/Eleanor_Maguire Eleanor A. Maguire] ('''2005'''). ''[http://www.jneurosci.org/content/25/31/7254.short The Human Hippocampus: Cognitive Maps or Relational Memory]?'' [https://en.wikipedia.org/wiki/The_Journal_of_Neuroscience Journal of Neuroscience], Vol. 25, No. 31
* [[Guillermo Campitelli]], [[Fernand Gobet]], Amanda Parker ('''2005'''). ''Structure and Stimulus Familiarity: A Study of Memory in Chess-Players with Functional Magnetic Resonance Imaging''. The Spanish Journal of Psychology Vol. 8, No. 2, 238-245. [http://www.estudiodepsicologia.com.ar/articles/4.pdf pdf]
* [[Alan H. Bond]] ('''2005'''). ''Representing episodic memory in a system-level model of the brain''. [http://www.elsevier.com/wps/find/journaldescription.cws_home/505628/description#description Neurocomputing], vol 65-66, pp. 261-273, [http://www.exso.com/cns04/cns04b_pub.pdf pdf]
* [[Guillermo Campitelli]], [[Fernand Gobet]], [http://www.nottingham.ac.uk/neuroscience/contact/a-z/G-L/head_kay.phtml Kay Head], [http://www.neuroscience.ox.ac.uk/directory/mark-buckley Mark Buckley], Amanda Parker ('''2007'''). ''Brain localisation of memory chunks in chessplayers.'' International Journal of Neuroscience, 117
* [[Dharshan Kumaran]] ('''2008'''). ''Short-Term Memory and The Human Hippocampus''. [https://en.wikipedia.org/wiki/The_Journal_of_Neuroscience Journal of Neuroscience], Vol. 28, No. 15, [https://drive.google.com/file/d/0B-Nvsz4idhaeUU9vVEV5QkpXZlk/view pdf]
* [[Demis Hassabis]] ('''2009'''). ''The Neural Processes Underpinning Episodic Memory''. Ph.D. thesis, [https://en.wikipedia.org/wiki/University_College_London University College London], Supervisor [https://en.wikipedia.org/wiki/Eleanor_Maguire Eleanor A. Maguire], [http://static1.1.sqspcdn.com/static/f/1096238/22752296/1369317078327/DemisHassabisThesis.pdf pdf]
=Forum Posts=
==1995 ...==
* [http://groups.google.com/group/rec.games.chess.computer/browse_frm/thread/dd8e54508bef37dd/ cache sizes] by [[Tom Kerrigan]], [[Computer Chess Forums|rgcc]], August 12, 1997
==2000 ...==
* [https://www.stmintz.com/ccc/index.php?id=293626 Difference in chess between DDR and PC133 SDRAM?] by [[Javier Ros Padilla]], [[CCC]], April 16, 2003
* [https://www.stmintz.com/ccc/index.php?id=306858 Another memory latency test] by [[Dieter Bürssner]], [[CCC]], July 17, 2003
* [http://groups.google.com/group/comp.lang.asm.x86/msg/26c662942c961ecd Re: Static memory allocation] by [[Matt Taylor]], [http://groups.google.com/group/comp.lang.asm.x86/topics comp.lang.asm.x86], July 03, 2004
==2005 ...==
* [http://www.talkchess.com/forum/viewtopic.php?t=21233 Minimizing Sharing of Data between Physical Processors] by [[Pradu Kannan]], [[CCC]], May 19, 2008
* [http://www.talkchess.com/forum/viewtopic.php?t=27229 malloc more than 2GB ?] by [[Frank Phillips]], [[CCC]], March 28, 2009
* [http://www.talkchess.com/forum/viewtopic.php?topic_view=threads&p=285407 Cache pollution when reading/writing hash table] by [[Marco Costalba]], [[CCC]], August 09, 2009
* [http://www.talkchess.com/forum/viewtopic.php?t=29434 Questions on volatile keyword and memory barriers] by [[Pradu Kannan]], [[CCC]], August 16, 2009
==2010 ...==
* [http://www.talkchess.com/forum/viewtopic.php?t=36516 Is a querying the hash tables such a huge bottleneck?] by [[Oliver Uwira]], [[CCC]], October 28, 2010
'''2011'''
* [http://www.talkchess.com/forum/viewtopic.php?t=38441 MSVC calloc question] by [[Harm Geert Muller]], [[CCC]], March 17, 2011
'''2012'''
* [http://www.talkchess.com/forum/viewtopic.php?t=44826 DNA data storage breaks records] by Terry McCracken, [[CCC]], August 18, 2012 <ref>[https://en.wikipedia.org/wiki/George_Church George Church], [http://www.bme.jhu.edu/people/primary.php?id=1045 Yuan Gao], [http://openwetware.org/wiki/Sriram_Kosuri Sriram Kosuri] ('''2012'''). ''[http://www.sciencemag.org/content/early/2012/08/15/science.1226355 Next-Generation Digital Information Storage in DNA]''. [https://en.wikipedia.org/wiki/Science_%28journal%29 Science]</ref>
'''2013'''
* [http://www.talkchess.com/forum/viewtopic.php?t=46968 DrMemory: memory debugger tool for Windows (and Linux)] by [[Martin Sedlak]], [[CCC]], January 22, 2013 » [[Debugging]]
* [http://www.open-chess.org/viewtopic.php?f=5&t=2262 Multi-threaded memory access] by [[Vadim Demichev|ThinkingALot]], [[Computer Chess Forums|OpenChess Forum]], February 10, 2013 » [[Thread]], [[Shared Hash Table]]
* [http://www.talkchess.com/forum/viewtopic.php?t=47706 Hybrid Memory Cube effect on computer chess] by [[Albert Silver]], [[CCC]], April 05, 2013 <ref>[https://en.wikipedia.org/wiki/Hybrid_Memory_Cube Hybrid Memory Cube from Wikipedia]</ref>
* [http://www.talkchess.com/forum/viewtopic.php?t=49388 MEM_LARGE_PAGES] by [[Alvaro Cardoso]], [[CCC]], September 18, 2013
* [http://www.talkchess.com/forum/viewtopic.php?t=49592 Multithreaded LRU] by [[Alvaro Cardoso]], [[CCC]], October 06, 2013 » [[Endgame Tablebases]]
* [http://www.talkchess.com/forum/viewtopic.php?t=49702 tablebase caching / mmap() / page cache] by [[Ronald de Man]], [[CCC]], October 13, 2013 » [[Endgame Tablebases]], [[Syzygy Bases]]
* [http://www.talkchess.com/forum/viewtopic.php?t=50334 Table Base Cache Size question] by Rob Nicholas, [[CCC]], December 05, 2013 » [[Endgame Tablebases]]
'''2014'''
* [http://www.talkchess.com/forum/viewtopic.php?t=51087 Intel i3 L2 cache] by [[Harm Geert Muller]], [[CCC]], January 28, 2014 » [[x86-64]] <ref>[https://en.wikipedia.org/wiki/Intel_Core#Core_i3 Intel Nehalem Core i3]</ref>
* [http://www.talkchess.com/forum/viewtopic.php?t=51824 c++11 std::atomic and memory_order_relaxed] by Kevin Hearn, [[CCC]], April 01, 2014 » [[Cpp|C++]]
* [http://www.talkchess.com/forum/viewtopic.php?t=53849 Speculative prefetch] by [[Peter Österlund]], [[CCC]], September 27, 2014 » [[Transposition Table]]
* [http://www.talkchess.com/forum/viewtopic.php?t=54064 Tablebase access using a Solid State Disk] by [[Steven Edwards]], [[CCC]], October 16, 2014 » [[Endgame Tablebases]]
* [http://www.talkchess.com/forum/viewtopic.php?t=54636 USB 3 Storage for Syzygy WDL files] by [[Louis Zulli]], [[CCC]], December 13, 2014 » [[Syzygy Bases]], [[Memory#USB3|USB 3.0]]
==2015 ...==
* [http://www.talkchess.com/forum/viewtopic.php?t=55132 Low-RAM engine] by [[Harm Geert Muller]], [[CCC]], January 28, 2015
* [http://www.talkchess.com/forum/viewtopic.php?t=55516 The effect of dual channel RAM] by [[Volker Annuss]], [[CCC]], March 01, 2015 » [[Arminius]]
* [http://www.talkchess.com/forum/viewtopic.php?t=56856 One hundred thirty gigabytes] by [[Steven Edwards]], [[CCC]], July 03, 2015
* [http://www.talkchess.com/forum/viewtopic.php?t=57149 3D XPoint] by [[Edmund Moshammer]], [[CCC]], August 02, 2015 <ref>[https://en.wikipedia.org/wiki/3D_XPoint 3D XPoint from Wikipedia]</ref>
* [http://www.talkchess.com/forum/viewtopic.php?t=57924 Hash cache] by [[Harm Geert Muller]], [[CCC]], October 12, 2015 » [[Hash Table]], [[Transposition Table]]
'''2016'''
* [http://www.talkchess.com/forum/viewtopic.php?t=58830 NUMA 101] by [[Robert Hyatt]], [[CCC]], January 07, 2016 » [[Parallel Search]]
* [http://www.talkchess.com/forum/viewtopic.php?t=60875 NUMA in a YBWC implementation] by [[Edsel Apostol]], [[CCC]], July 20, 2016 » [[Young Brothers Wait Concept]]
* [https://groups.google.com/d/msg/fishcooking/ezt6MrAuXqs/qIR2HEciEgAJ lets get the ball moving down the field on numa awareness] by [[Mohammed Li]], [[Computer Chess Forums|FishCooking]], August 30, 2016 » [[NUMA]], [[Stockfish]], [[asmFish]]
* [http://www.talkchess.com/forum/viewtopic.php?t=61423 Tipical cache and branch misses for a chess engine] by [[Nicu Ionita]], [[CCC]], September 14, 2016 » [[Avoiding Branches]], [[Profiling]]
* [http://www.talkchess.com/forum/viewtopic.php?t=61472 What do you do with NUMA?] by [[Matthew Lai]], [[CCC]], September 19, 2016 » [[NUMA]]
* [http://rybkaforum.net/cgi-bin/rybkaforum/topic_show.pl?tid=31867 L3 cache, RAM and other performance factors] by Nimzy, [[Computer Chess Forums|Rybka Forum]], December 04, 2016 » [[Playing Strength]]
'''2017'''
* [http://www.talkchess.com/forum/viewtopic.php?t=63652 6-men Syzygy from HDD and USB 3.0] by [[Kai Laskos]], [[CCC]], April 04, 2017 » [[Komodo]], [[Playing Strength]], [[Syzygy Bases]], [[Memory#USB3|USB 3.0]]
* [http://www.talkchess.com/forum/viewtopic.php?t=63886 RAM speed and engine strength] by John Hartmann, [[CCC]], May 03, 2017 » [[Memory#RAM|RAM]], [[Playing Strength]]
* [http://www.talkchess.com/forum/viewtopic.php?t=65284 Probing tablebases through USB 3.0] by [[Jon Fredrik Åsvang]], [[CCC]], September 25, 2017 » , [[Syzygy Bases]], [[Memory#USB3|USB 3.0]]
=External Links=
* [https://en.wikipedia.org/wiki/Memory_%28disambiguation%29 Memory (disambiguation) from Wikipedia]
==Computer Memory==
* [http://ljkrakauer.com/LJK/essays/bits.htm Bits] by [[Lawrence J. Krakauer]]
* [https://en.wikipedia.org/wiki/Computer_memory Computer memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Data_dictionary Data dictionary from Wikipedia]
* [https://en.wikipedia.org/wiki/Lookup_table Lookup table from Wikipedia]
* [http://ljkrakauer.com/LJK/60s/moby.htm Moby Memory] by [[Lawrence J. Krakauer]] » [[PDP-6]]
* [https://en.wikipedia.org/wiki/Multi-level_Cell Multi-level cell from Wikipedia]
* <span id="Semiconductor"></span>[https://en.wikipedia.org/wiki/Semiconductor_memory Semiconductor memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Universal_memory Universal memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Von_Neumann_architecture Von Neumann architecture from Wikipedia]
==Gustavo Duarte's Blog==
from [http://duartes.org/gustavo/blog/best-of Best Of] by [http://duartes.org/gustavo/blog/ Gustavo Duarte]:
* [http://duartes.org/gustavo/blog/post/motherboard-chipsets-memory-map Motherboard Chipsets and the Memory Map]
* [http://duartes.org/gustavo/blog/post/anatomy-of-a-program-in-memory Anatomy of a Program in Memory]
* [http://duartes.org/gustavo/blog/post/how-the-kernel-manages-your-memory How The Kernel Manages Your Memory]
* [http://duartes.org/gustavo/blog/post/page-cache-the-affair-between-memory-and-files Page Cache, the Affair Between Memory and Files]
* [http://duartes.org/gustavo/blog/post/memory-translation-and-segmentation Memory Translation and Segmentation]
* [http://duartes.org/gustavo/blog/post/getting-physical-with-memory Getting Physical With Memory]
* [http://duartes.org/gustavo/blog/post/cpu-rings-privilege-and-protection CPU Rings, Privilege, and Protection]
* [http://duartes.org/gustavo/blog/post/intel-cpu-caches Cache: a place for concealment and safekeeping]
* [http://duartes.org/gustavo/blog/post/the-thing-king The Thing King]
==[[Cognition]]==
* [https://en.wikipedia.org/wiki/Cognition Cognition from Wikipedia]
* [http://en.wikibooks.org/wiki/Cognitive_Psychology_and_Cognitive_Neuroscience/Memory Cognitive Psychology and Cognitive Neuroscience/Memory from Wikibooks]
* [https://en.wikipedia.org/wiki/Long-term_memory Long-term memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Memory Memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Recall_%28memory%29 Recall (memory) from Wikipedia]
* [https://en.wikipedia.org/wiki/Short-term_memory Short-term memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Working_memory Working memory from Wikipedia]
==Neuroscience==
* [https://en.wikipedia.org/wiki/Neuroscience Neuroscience from Wikipedia]
* [https://en.wikipedia.org/wiki/Biological_neural_network Biological neural network from Wikipedia]
* [https://en.wikipedia.org/wiki/Brain Brain from Wikipedia]
* [https://en.wikipedia.org/wiki/Cognitive_neuroscience Cognitive neuroscience from Wikipedia]
* [http://www.fourmilab.ch/documents/comp_mem_nat_life/ Computation, Memory, Nature, and Life] - Is digital storage the secret of life? by [https://en.wikipedia.org/wiki/John_Walker_%28programmer%29 John Walker]
* [https://en.wikipedia.org/wiki/Human_brain Human brain from Wikipedia]
* [http://en.wikiversity.org/wiki/Memory_%28biological%29 Memory (biological)] from [http://en.wikiversity.org/wiki/Wikiversity:Main_Page Wikiversity]
==Misc==
* [https://en.wikipedia.org/wiki/Art_of_memory Art of memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Electric_Fence Electric Fence (Memory Debugger) from Wikipedia] » [[Debugging]]
* [https://en.wikipedia.org/wiki/Mnemonic Mnemonic from Wikipedia]
* [https://en.wikipedia.org/wiki/Moore%27s_law Moore's law from Wikipedia]
* [https://en.wikipedia.org/wiki/Paper_data_storage Paper data storage from Wikipedia]
* [[Videos#AlDiMeola|Al Di Meola]], [[Videos#StanleyClarke|Stanley Clarke]], [[Videos#JeanLucPonty|Jean luc Ponty]] - [https://en.wikipedia.org/wiki/The_Rite_of_Strings Memory Canyon], [https://en.wikipedia.org/wiki/Montreux_Jazz_Festival Montreux] 1994, [https://en.wikipedia.org/wiki/YouTube YouTube] Video
: {{#evu:https://www.youtube.com/watch?v=bRe0IhgJ2W8|alignment=left|valignment=top}}
=References=
<references />
'''[[Hardware|Up one Level]]'''
[[FILE:RNA-comparedto-DNA thymineAndUracilCorrected.png|border|right|thumb|[https://en.wikipedia.org/wiki/RNA RNA], biological [https://en.wikipedia.org/wiki/Data_storage_device data storage] <ref>[https://en.wikipedia.org/wiki/Data_storage_device Data storage device from Wikipedia]</ref> ]]
'''Memory''' is the ability to [https://en.wikipedia.org/wiki/Store store], retain, and [https://en.wikipedia.org/wiki/Recall_%28memory%29 recall] [https://en.wikipedia.org/wiki/Information information] and [https://en.wikipedia.org/wiki/Experience experiences] as researched in [[Cognition|cognitive science]]. Computer memory refers to [https://en.wikipedia.org/wiki/Peripheral physical devices] used to store [[Data|data]] and sequences of instructions ([[Program|programs]]) on a temporary or permanent basis, typically distinguished as fast [https://en.wikipedia.org/wiki/Random_access_memory random-access memory] and relatively slow [https://en.wikipedia.org/wiki/Computer_data_storage data storage].
<span id="FlipFlop"></span>
=Flip-Flop=
A [https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29 flip-flop] or [https://en.wikipedia.org/wiki/Latch_%28electronics%29 latch] is a one [[Bit|bit]] memory. For instance a simple [https://en.wikipedia.org/wiki/Relay relay] (K1) with its contact parallel to the On-push-button S2, "remembers" whether last action was pushing S1 (reset) or S2 (set) <ref>[http://de.wikipedia.org/wiki/Selbsthaltefunktion Selbsthaltefunktion from Wikidepia.de] (German)</ref> .
[[FILE:Selbsthaltung.gif|none|border|text-bottom]]
A [https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#RS_.28Reset-Set.29_flip-flop RS flip-flop] is a pair of cross-coupled [[Combinatorial Logic#NAND|NAND]] or [[Combinatorial Logic#NOR|NOR-gates]], where the outputs are feed back to the inputs. A [https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#D_.28Delay.29_flip-flop D flip-flop], the most common flip-flop, stores the input D with the rising edge (0-1 transition) of a clock.
{| class="wikitable"
|-
! RS flip-flop
! D flip-flop
! Discrete
|-
| [[FILE:RS flipflop.svg|none|border|text-bottom|220px]]
| [[FILE:D-Type Flip-flop.svg|none|border|text-bottom|180px]]
| rowspan="2=" | [[FILE:flipflop6as.jpg|none|border|text-bottom|260px|link=http://ljkrakauer.com/LJK/essays/bits.htm]]
|-
| [[FILE:R-S mk2.gif|none|border|text-bottom|220px]]
| [[FILE:Edge triggered D flip flop.svg|none|border|text-bottom|180px]]
|-
| from two NOR (red == 1) <ref>[https://en.wikipedia.org/wiki/Latch_%28electronics%29 Latch (electronics) from Wikipedia]</ref>
| from six NAND <ref>[https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29 Flip-flop (electronics) from Wikipedia]</ref>
| [[PDP-6]] flip-flop <ref>[http://ljkrakauer.com/LJK/essays/bits.htm Bits] by [[Lawrence J. Krakauer]]</ref> <ref>[http://bitsavers.trailing-edge.com/pdf/dec/pdp6/F-67_circuitInstr_May66.pdf PDP-6 Circuit Instruction Manual, © 1966, Digital Equipment Corporation] (pdf)</ref>
|}
* [https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29 Flip-flop (electronics) from Wikipedia]
* [https://en.wikipedia.org/wiki/Latch_%28electronics%29 Latch (electronics) from Wikipedia]
<span id="Latches"></span>
=N-Bit Latches=
N-Bit latches are [[Array|arrays]] of one-bit latches or flip-flops typically as wide as a connected parallel [https://en.wikipedia.org/wiki/Bus_%28computing%29 data-bus]. They may be used as a [https://en.wikipedia.org/wiki/Processor_register registers] or [https://en.wikipedia.org/wiki/Scratchpad_RAM scratchpad RAM] inside a [https://en.wikipedia.org/wiki/CPU central processing unit].
<span id="RAM"></span>
=RAM=
[https://en.wikipedia.org/wiki/Random_access_memory Random access memory] is a fast form of computer memory and refers to the idea that any piece of [[Data|data]] can be stored and retrieved in a constant time, regardless of its physical location and whether or not it is related to the previous piece of data.
* [https://en.wikipedia.org/wiki/Random_access_memory Random-access memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Volatile_memory Volatile memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Phase-change_memory Phase-change memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Ferroelectric_RAM Ferroelectric RAM from Wikipedia]
<span id="StaticRAM"></span>
==Static RAM==
[https://en.wikipedia.org/wiki/Static_random_access_memory Static RAM] (SRAM) is an array of latches, where each latch has a unique [https://en.wikipedia.org/wiki/Memory_address address], which connects the addressed latch to its [https://en.wikipedia.org/wiki/Bus_%28computing%29 data-bus], often used as [https://en.wikipedia.org/wiki/Cache#CPU_cache CPU cache].
* [https://en.wikipedia.org/wiki/Static_random_access_memory Static random access memory from Wikipedia]
<span id="DynamicRAM"></span>
==Dynamic RAM==
[https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory] (DRAM) is a type of random access memory that stores each bit of data in a separate [https://en.wikipedia.org/wiki/Capacitor capacitor] within an electronic circuit. Since capacitors leak charge, the information eventually fades unless the capacitor charge is [https://en.wikipedia.org/wiki/Memory_refresh refreshed] periodically, which is the reason to call that memory dynamic. Since DRAM takes only one [https://en.wikipedia.org/wiki/Transistor transistor] and capacitor per bit, it is therefor used as cheap main memory part of recent [https://en.wikipedia.org/wiki/Computer_data_storage computer data storage], despite its worse latency compared to SRAM.
* [https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory from Wikipedia]
: [https://en.wikipedia.org/wiki/SDRAM Synchronous dynamic random access memory (SDRAM)]
: [https://en.wikipedia.org/wiki/DDR_SDRAM DDR SDRAM] with [https://en.wikipedia.org/wiki/Double_data_rate Double data rate]
* [https://en.wikipedia.org/wiki/Interleaved_memory Interleaved memory]
* [https://en.wikipedia.org/wiki/SDRAM_latency SDRAM latency]
* [https://en.wikipedia.org/wiki/CAS_latency CAS latency]
* [https://en.wikipedia.org/wiki/Memory_controller Memory controller]
* [https://en.wikipedia.org/wiki/Memory_geometry Memory geometry]
* [https://en.wikipedia.org/wiki/Hybrid_Memory_Cube Hybrid Memory Cube]
[[FILE:Square array of mosfet cells read.png|none|border|text-bottom|480px]]
DRAM write at a 4 by 4 array <ref>[https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory from Wikipedia]</ref>
<span id="ROM"></span>
=ROM=
[https://en.wikipedia.org/wiki/Read-only_memory Read-only memory] (ROM) is a class of storage programmed once and mainly used to distribute [https://en.wikipedia.org/wiki/Firmware firmware]. [https://en.wikipedia.org/wiki/EPROM EPROMs] have a small quartz window which admits UV light for erasure <ref>[http://www.6502.org/users/dallas/SYM/SYM%20Projects/2716-2532%20EPROM%20BURNER/2716-2532.htm How to program a 2716]</ref> . ROM or EPROM were often embedded inside a [https://en.wikipedia.org/wiki/Microcontroller microcontroller] in conjunction with some RAM. They were often used in [[Dedicated Chess Computers|dedicated chess computers]].
[[FILE:EPROMs National Semiconductor.jpg|none|border|480px]]
[https://en.wikipedia.org/wiki/National_Semiconductor National Semiconductor] [https://en.wikipedia.org/wiki/EPROM#EPROM_generations,_sizes_and_types EPROMs 2764 and 2716] <ref>[https://commons.wikimedia.org/wiki/Category:EPROM_2716 Category:EPROM 2716 - Wikimedia Commons]</ref>
Since each data-bit stored in a ROM is a boolean function of its inputs or address, a ROM is also used to implement [[Combinatorial Logic|combinatorial logic]].
* [https://en.wikipedia.org/wiki/Read-only_memory Read-only memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Non-volatile_memory Non-volatile memory from Wikipedia]
=Auxiliary Storage=
Beside the computer's random access main memory, [https://en.wikipedia.org/wiki/Computer_data_storage auxiliary storage] refer to [https://en.wikipedia.org/wiki/Mass_storage mass storage] like [https://en.wikipedia.org/wiki/Optical_disc optical discs], and [https://en.wikipedia.org/wiki/Magnetic_storage magnetic storage] [https://en.wikipedia.org/wiki/Hard_disk_drive hard disk drives]. Those devices are usually connected via a [https://en.wikipedia.org/wiki/Serial_communication serial] bus, and accessed via [https://en.wikipedia.org/wiki/Stream_%28computing%29 streams].
[[FILE:Intelligent_Chess_1_20x20.JPG|none|border|text-bottom|480px|link=http://www.chesscomputeruk.com/html/intelligent_chess.html]]
[https://en.wikipedia.org/wiki/Compact_Cassette Compact Cassette] as Auxiliary Storage in [[Intelligent Chess]] <ref>[http://www.chesscomputeruk.com/html/intelligent_chess.html Intelligent Chess] from [http://www.chesscomputeruk.com/index.html Chess Computer UK] by [[Mike Watters]]</ref>
* [https://en.wikipedia.org/wiki/Computer_data_storage Computer data storage from Wikipedia]
* [https://en.wikipedia.org/wiki/Computer_data_storage Auxiliary storage]
* [https://en.wikipedia.org/wiki/Mass_storage Mass storage]
* [https://en.wikipedia.org/wiki/Magnetic_storage Magnetic storage]
* [https://en.wikipedia.org/wiki/Magnetic_tape_data_storage Magnetic tape data storage]
* [https://en.wikipedia.org/wiki/Floppy_disk Floppy disk]
* [https://en.wikipedia.org/wiki/Hard_disk_drive Hard disk drive]
* [https://en.wikipedia.org/wiki/RAID RAID]
* [https://en.wikipedia.org/wiki/Optical_disc Optical discs]
* [https://en.wikipedia.org/wiki/Compact_Disc Compact Disc]
* [https://en.wikipedia.org/wiki/DVD DVD]
* [https://en.wikipedia.org/wiki/Blu-ray_Disc Blu-ray Disc]
* [https://en.wikipedia.org/wiki/Solid-state_drive Solid-state drive]
* <span id="Flash"></span>[https://en.wikipedia.org/wiki/Flash_memory Flash memory]
* [https://en.wikipedia.org/wiki/USB_flash_drive USB flash drive]
: <span id="USB3"></span>[https://en.wikipedia.org/wiki/USB_3.0 USB 3.0]
* [https://en.wikipedia.org/wiki/Memory_Stick Memory Stick]
* [https://en.wikipedia.org/wiki/Memory_card Memory card]
* [https://en.wikipedia.org/wiki/Secure_Digital Secure Digital (SD)]
* [https://en.wikipedia.org/wiki/Serial_ATA Serial ATA]
* [https://en.wikipedia.org/wiki/Parallel_ATA Parallel ATA]
* [https://en.wikipedia.org/wiki/3D_XPoint 3D XPoint from Wikipedia] <ref>[http://www.talkchess.com/forum/viewtopic.php?t=57149 3D XPoint] by [[Edmund Moshammer]], [[CCC]], August 02, 2015</ref>
=Historical Data Storage=
* [https://en.wikipedia.org/wiki/History_of_computing_hardware History of computing hardware from Wikipedia]
* [http://www.columbia.edu/acis/history/tubes.html Vacuum Tube Memory] from [http://www.columbia.edu/acis/history/index.html Columbia University Computing History]
* [https://en.wikipedia.org/wiki/Selectron_tube Selectron tube from Wikipedia]
* [https://en.wikipedia.org/wiki/Williams_tube Williams tube from Wikipedia]
* <span id="Core"></span>[https://en.wikipedia.org/wiki/Magnetic_core_memory Magnetic-core memory from Wikipedia]
: [[FILE:Coincident-current magnetic core.svg|none|border|text-bottom|320px]]
: <span id="Plated"></span>[https://en.wikipedia.org/wiki/Plated_wire_memory Plated wire memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Punched_card Punched card from Wikipedia]
* [https://en.wikipedia.org/wiki/Punched_tape Punched tape from Wikipedia]
* [https://en.wikipedia.org/wiki/Drum_memory Drum memory from Wikipedia]
: [[FILE:Pamiec bebnowa 1.jpg|none|border|text-bottom|320px]]
* [https://en.wikipedia.org/wiki/Delay_line_memory Delay line memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Magnetic_bubble_memory Bubble memory from Wikipedia]
=Memory Hierarchy=
* [https://en.wikipedia.org/wiki/Memory_hierarchy Memory hierarchy from Wikipedia]
: [[FILE:ComputerMemoryHierarchy.svg|none|border|text-bottom|640px|link=https://en.wikipedia.org/wiki/Memory_hierarchy]]
* [https://en.wikipedia.org/wiki/Memory_organisation Memory organisation from Wikipedia]
<span id="Management"></span>
=Memory Management=
Todays processors utilize all the above types of memory from small and fast to large but slow within the concepts of [https://en.wikipedia.org/wiki/Virtual_memory virtual memory], [https://en.wikipedia.org/wiki/Paging paging], [https://en.wikipedia.org/wiki/Memory_protection protection] and various [https://en.wikipedia.org/wiki/Cache caches].
* [https://en.wikipedia.org/wiki/Memory_management Memory management from Wikipedia]
* [https://en.wikipedia.org/wiki/Memory_management_unit Memory management unit from Wikipedia]
* [http://msdn.microsoft.com/en-us/library/aa366779%28v=VS.85%29.aspx MSDN - Memory Management] » [[Windows]]
* [http://www.memorymanagement.org/ The Memory Management Reference] [http://www.ravenbrook.com/ Ravenbrook]
* [https://en.wikipedia.org/wiki/Memory_protection Memory protection from Wikipedia]
<span id="Virtual"></span>
==Virtual Memory==
{|
|-
| [[FILE:Page table actions.svg|none|border|text-bottom|460px]]
| [[FILE:Virtual address space and physical address space relationship.svg|none|border|text-bottom|320px]]
|-
| [https://en.wikipedia.org/wiki/Physical_address Physical address] translation <ref>[https://en.wikipedia.org/wiki/Page_table Page table from Wikipedia]</ref>
| Virtual and physical address space <ref>[https://en.wikipedia.org/wiki/Virtual_address Virtual address from Wikipedia]</ref>
|}
* [https://en.wikipedia.org/wiki/Virtual_memory Virtual memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Memory_address Memory address from Wikipedia]
* [https://en.wikipedia.org/wiki/Physical_address Physical address from Wikipedia]
* [https://en.wikipedia.org/wiki/Virtual_address Virtual address from Wikipedia]
* [https://en.wikipedia.org/wiki/VAX Virtual Address eXtension (VAX) from Wikipedia]
<span id="Page"></span>
==Paging==
* [https://en.wikipedia.org/wiki/Page_%28computer_memory%29 Page (computer memory) from Wikipedia]
: [https://en.wikipedia.org/wiki/Page_table Page table]
: [https://en.wikipedia.org/wiki/Page_replacement_algorithm Page replacement algorithm]
: <span id="Paging"></span>[https://en.wikipedia.org/wiki/Paging Paging]
: [https://en.wikipedia.org/wiki/Demand_paging Demand Paging]
: [https://en.wikipedia.org/wiki/Page_fault Page fault]
: [https://en.wikipedia.org/wiki/Copy-on-write Copy-on-write]
<span id="TLB"></span>
==TLB==
* [https://en.wikipedia.org/wiki/Translation_Lookaside_Buffer Translation lookaside buffer (TLB)]
<span id="HugePages"></span>
==Huge Pages==
''Note that what [[Windows]] calls "large pages," [[Linux]] and [[Unix]] call "huge pages" or "huge TLB pages'' ([[x86]] and [[x86-64]])
* [https://en.wikipedia.org/wiki/Page_Size_Extension Page Size Extension from Wikipedia]
* [http://msdn.microsoft.com/en-us/library/aa366720%28v=vs.85%29.aspx MSDN - Large-Page Support] » [[Windows]]
* [http://lwn.net/Articles/374424/ Huge pages part 1 Introduction] by [http://www.csn.ul.ie/%7Emel/blog/index.php?/authors/1-Mel-Gorman Mel Gorman], [https://en.wikipedia.org/wiki/LWN.net LWN.net], February 16, 2010 » [[Linux]]
* [http://lwn.net/Articles/375096/ Huge pages part 2: Interfaces] by [http://www.csn.ul.ie/%7Emel/blog/index.php?/authors/1-Mel-Gorman Mel Gorman], [https://en.wikipedia.org/wiki/LWN.net LWN.net], February 24, 2010
* [http://lwn.net/Articles/376606/ Huge pages part 3: Administration] by [http://www.csn.ul.ie/%7Emel/blog/index.php?/authors/1-Mel-Gorman Mel Gorman], [https://en.wikipedia.org/wiki/LWN.net LWN.net], March 3, 2010
* [http://lwn.net/Articles/378641/ Huge pages part 4: benchmarking with huge pages] by [http://www.csn.ul.ie/%7Emel/blog/index.php?/authors/1-Mel-Gorman Mel Gorman], [https://en.wikipedia.org/wiki/LWN.net LWN.net], March 17, 2010
* [http://lwn.net/Articles/379748/ Huge pages part 5: A deeper look at TLBs and costs] by [http://www.csn.ul.ie/%7Emel/blog/index.php?/authors/1-Mel-Gorman Mel Gorman], [https://en.wikipedia.org/wiki/LWN.net LWN.net], March 23, 2010
* [http://lwn.net/Articles/423584/ Transparent huge pages in 2.6.38] by [http://kerneltrap.org/Jonathan_Corbet Jonathan Corbet], [https://en.wikipedia.org/wiki/LWN.net LWN.net], January 19, 2011
=Memory Model=
* [https://en.wikipedia.org/wiki/Memory_model_%28computing%29 Memory model (computing) from Wikipedia]
* [https://en.wikipedia.org/wiki/Consistency_model Consistency model from Wikipedia]
* [https://en.wikipedia.org/wiki/Memory_ordering Memory ordering from Wikipedia]
* [https://en.wikipedia.org/wiki/Memory_barrier Memory barrier from Wikipedia]
* [https://en.wikipedia.org/wiki/Flat_memory_model Flat memory model from Wikipedia]
* [https://en.wikipedia.org/wiki/Intel_Memory_Model Intel Memory Model from Wikipedia] » [[Intel]], [[x86]], [[C]], [[Cpp|C++]]
* [https://en.wikipedia.org/wiki/Java_Memory_Model Java Memory Model from Wikipedia] » [[Java]]
* [http://www.hpl.hp.com/personal/Hans_Boehm/c++mm/ Threads and memory model for C++] by [http://www.hpl.hp.com/personal/Hans_Boehm/ Hans J. Boehm]
* [http://golang.org/doc/go_mem.html The Go Memory Model] » [[Go (Programming Language)]]
<span id="Shared"></span>
==Shared Memory==
{{Shared Memory}}
==<span id="Cache"></span>Cache==
{{Cache}}
==Segmentation==
* [https://en.wikipedia.org/wiki/Memory_segmentation Memory segmentation from Wikipedia]
* [https://en.wikipedia.org/wiki/Data_segment Data segment]
* [https://en.wikipedia.org/wiki/.bss .bss]
* [https://en.wikipedia.org/wiki/Code_segment Code segment]
* [https://en.wikipedia.org/wiki/Segmentation_fault Segmentation fault]
* [https://en.wikipedia.org/wiki/SIGSEGV SIGSEGV]
* [https://en.wikipedia.org/wiki/X86_memory_segmentation x86 memory segmentation] » [[x86]]
* [http://software.intel.com/en-us/articles/memory-limits-applications-windows/ Memory Limits for Applications on Windows] by [http://software.intel.com/en-us/user/512685 Steve Lionel] ([[Intel]]), May 16, 2011» [[Windows]]
==Allocation==
* [https://en.wikipedia.org/wiki/Dynamic_memory_allocation Dynamic memory allocation from Wikipedia]
: [https://en.wikipedia.org/wiki/Manual_memory_management Manual memory management]
: [https://en.wikipedia.org/wiki/Memory_leak Memory leak]
: [https://en.wikipedia.org/wiki/Garbage_collection_%28computer_science%29 Garbage collection]
* [https://en.wikipedia.org/wiki/Stack-based_memory_allocation Stack-based memory allocation] » [[Stack]]
* [https://en.wikipedia.org/wiki/Buddy_memory_allocation Buddy memory allocation]
* [https://en.wikipedia.org/wiki/Hoard_memory_allocator Hoard memory allocator]
* [https://en.wikipedia.org/wiki/Memory_pool Memory pool]
<span id="Footprint"></span>
=Memory Footprint=
Beside their individual [https://en.wikipedia.org/wiki/Memory_footprint memory footprint], chess programs have to deal with huge memory areas of [[Transposition Table|transposition table]] and possibly caches for [[Endgame Tablebases|endgame table-]] or [[Endgame Bitbases|bitbases]] and their relative huge random access latencies.
* [https://en.wikipedia.org/wiki/Memory_footprint Memory footprint from Wikipedia]
* [http://www.freepatentsonline.com/y2007/0033371.html Method and apparatus for establishing a cache footprint for shared processor logical partitions]
* [https://en.wikipedia.org/wiki/Memory_timings Memory timings from Wikipedia]
* [https://en.wikipedia.org/wiki/Access_time Access time]
* [https://en.wikipedia.org/wiki/CAS_latency CAS latency]
* [https://en.wikipedia.org/wiki/Memory_bandwidth Memory bandwidth]
* [http://zsmith.co/bandwidth.html Bandwidth: a memory bandwidth benchmark for x86 / x86_64 based Linux/Windows/MacOSX] by Zack Smith
* [https://en.wikipedia.org/wiki/Cache_pollution Cache pollution]
* [https://en.wikipedia.org/wiki/Thrashing_%28computer_science%29 Thrashing (computer science)]
* [https://en.wikipedia.org/wiki/False_sharing False sharing from Wikipedia]
* [https://en.wikipedia.org/wiki/Miles_Davis_Quintet Miles Davis Quintet] - [https://en.wikipedia.org/wiki/Footprints_(composition) Footprints] ([[Videos#WayneShorter|Wayne Shorter]]), New York, 1966, [https://en.wikipedia.org/wiki/YouTube YouTube] Video
: [[Videos#MilesDavis|Miles Davis]], [[Videos#WayneShorter|Wayne Shorter]], [[Videos#HerbieHancock|Herbie Hancock]], [https://en.wikipedia.org/wiki/Ron_Carter Ron Carter], [https://en.wikipedia.org/wiki/Tony_Williams_(drummer) Tony Williams]
: {{#evu:https://www.youtube.com/watch?v=j7lkqxfvA78|alignment=left|valignment=top}}
* [http://krakowskascenamuzyczna.pl/tag/monika-malczak/ Monika Malczak Quartet] - [https://en.wikipedia.org/wiki/Footprints_(composition) Footprints], [http://www2.polskieradio.pl/studio/lutoslawski_en.aspx Witold Lutosławski Concert Studio of Polish Radio], [https://en.wikipedia.org/wiki/Warsaw Warsaw], May 20, 2016, [https://en.wikipedia.org/wiki/YouTube YouTube] Video
: [http://krakowskascenamuzyczna.pl/tag/monika-malczak/ Monika Malczak], [http://jazz.radionadzieja.pl/mateusz-gramburg-fortepian/ Mateusz Gramburg], [https://www.instagram.com/pure_o/ Paweł Zwierzyński-Pióro], [https://www.facebook.com/people/Micha%C5%82-Szeligowski/1505615273 Michał Szeligowski]
: {{#evu:https://www.youtube.com/watch?v=jpZ4B67xtII|alignment=left|valignment=top}}
=Multiprocessing=
* [[SMP]]
* [[NUMA]]
=Memory versus Search=
* [[Best-First]]
* [[Depth-First]]
* [[Endgame Tablebases]]
* [[Knowledge]]
* [[Learning]]
* [[MTD(f)]]
* [[Parallel Search]]
* [[Persistent Hash Table]]
* [[Space-Time Tradeoff]]
* [[SSS* and Dual*]]
* [[Transposition Table]]
=See also=
* [[Algorithms]]
* [[Array]]
* [[Cognition]]
* [[Combinatorial Logic]]
* [[Data]]
* [[Hash Table]]
* [[Psychology]]
* [[Queue]]
* [[Sequential Logic]]
* [[Shared Hash Table]]
* [[Stack]]
=Publications=
==Computer Memory==
===1960 ...===
* [https://en.wikipedia.org/wiki/Ken_Knowlton Kenneth C. Knowlton] ('''1965'''). ''A Fast storage allocator''. [[ACM#Communications|Communications of the ACM]], Vol. 8, No. 10 : 623-625
===1970 ...===
* [[Donald Eastlake]] ('''1977'''). ''[http://www.informatik.uni-trier.de/~ley/db/conf/vldb/Eastlake77.html Tertiary Memory Access and Performance in the Datacomputer]''. [http://www.informatik.uni-trier.de/~ley/db/conf/vldb/vldb77.html#Eastlake77 VLDB 1977]
===1980 ...===
* [[Ozalp Babaoglu]], [https://en.wikipedia.org/wiki/Bill_Joy William Joy] ('''1981'''). ''Converting a Swap-Based System to do Paging in an Architecture Lacking Page-Reference Bits''. Proceedings of the 8th SOSP, Operating Systems Review, Vol. 15, No. 5, pp. 78-86
* [[Bruce W. Leverett]], [http://genealogy.math.ndsu.nodak.edu/id.php?id=95738 Peter G. Hibbard] ('''1982'''). ''[http://onlinelibrary.wiley.com/doi/10.1002/spe.4380120606/abstract An Adaptive System for Dynamic Storage Allocation]''. [http://www.informatik.uni-trier.de/~ley/db/journals/spe/spe12.html#LeverettH82 Software: Practice and Experience], [http://onlinelibrary.wiley.com/doi/10.1002/spe.v12:6/issuetoc Vol. 12, No. 6], pp. 543-555
* [[Subir Bhattacharya]], [[Amitava Bagchi]] ('''1986'''). ''Making Best Use of Available Memory when Searching Game Trees.'' Proceedings of the 5th International Conference on Artificial Intelligence (AAAI-86), pp. 163-167. AAAI/MIT Press, Boston, MA.
===1990 ...===
* [[Peter W. Frey]] ('''1991'''). ''Memory-Based Expertise: Computer Chess vs. AI''. [[ICGA Journal#14_4|ICCA Journal, Vol. 14, No. 4]]
* [[Jos Uiterwijk]] ('''1992'''). ''Memory Efficiency in some Heuristics''. [[ICGA Journal#15_2|ICCA Journal, Vol. 15, No. 2]]
* [[Wim Pijls]], [[Arie de Bruin]] ('''1993'''). ''SSS*-like Algorithms in Constrained Memory.'' [[ICGA Journal#16_1|ICCA Journal, Vol. 16, No. 1]]
* [[Hermann Kaindl]], G. Kainz, A. Leeb, H. Smetana ('''1995'''). ''How to use limited memory in heuristic search''. Proceedings of the Fourteenth International Joint Conference on Artificial Intelligence (IJCAI-95), Montreal, Canada, pp. 236-242.
* [[Dennis Breuker]] ('''1998'''). ''Memory versus Search in Games''. Ph.D. thesis, [[Maastricht University]], pdf available via [http://www.dennisbreuker.nl/thesis/index.html Dennis Breuker's page]
* [[Harald Prokop]] ('''1999'''). ''Cache-Oblivious Algorithms''. Masters thesis, Department of Electrical Engineering and Computer Science, [[Massachusetts Institute of Technology|MIT]], [http://supertech.csail.mit.edu/papers/Prokop99.pdf pdf] <ref>[https://en.wikipedia.org/wiki/Cache-oblivious_algorithm Cache-oblivious algorithm from Wikipedia]</ref>
===2000 ...===
* [http://dblp.uni-trier.de/pers/hd/y/Yang:Yue Yue Yang], [http://dblp.uni-trier.de/pers/hd/g/Gopalakrishnan:Ganesh Ganesh Gopalakrishnan], [[Gary Lindstrom]] ('''2002'''). ''Specifying Java Thread Semantics Using a Uniform Memory Model''. [http://dblp.uni-trier.de/db/conf/java/java2002.html#YangGL02 Java Grande 2002], [http://formalverification.cs.utah.edu/yyang/papers/umm_old.pdf pdf]
* [[F. Warren Burton]], [http://dblp.uni-trier.de/pers/hd/s/Simpson:David_J= David J. Simpson] ('''2000'''). ''[http://www.sciencedirect.com/science/article/pii/S0167819100000533 Memory requirements for parallel programs]''. [http://www.journals.elsevier.com/parallel-computing/ Parallel Computing], Vol. 26, Nos. 13-14
* [[Mathematician#QWu|Qiang Wu]], [[Artem Petakov|Artem Pyatakov]], [[Mathematician#ASpiridonov|Alexey Spiridonov]], [http://liberty.princeton.edu/Publications/index.php?setselect=eraman Easwaran Raman], [[Mathematician#DWClark|Douglas W. Clark]], [[Mathematician#DIAugust|David I. August]] ('''2004'''). ''Exposing Memory Access Regularities Using Object-Relative Memory Profiling''. [http://dblp.uni-trier.de/db/conf/cgo/cgo2004.html#WuPSRCA04 CGO 2004], [http://www.cs.princeton.edu/~jqwu/orp_paper.pdf pdf]
* [http://de.wikipedia.org/wiki/Ulrich_Drepper Ulrich Drepper] ('''2007'''). ''What Every Programmer Should Know About Memory''. [http://www.akkadia.org/drepper/cpumemory.pdf pdf], also hosted by [https://en.wikipedia.org/wiki/LWN.net LWN.net]
: [http://lwn.net/Articles/250967/ Memory part 1]
: [http://lwn.net/Articles/252125/ Memory part 2: CPU caches]
: [http://lwn.net/Articles/253361/ Memory part 3: Virtual Memory]
: [http://lwn.net/Articles/254445/ Memory part 4: NUMA support]
: [http://lwn.net/Articles/255364/ Memory part 5: What programmers can do]
* [[David Silver]], [[Richard Sutton]], [[Martin Müller]] ('''2008'''). ''Sample-Based Learning and Search with Permanent and Transient Memories''. In Proceedings of the 25th International Conference on Machine Learning, [http://webdocs.cs.ualberta.ca/%7Esilver/David_Silver/Publications_files/dyna2.pdf pdf]
===2010 ...===
* [[Aaron Becker]], [http://charm.cs.uiuc.edu/people/gengbinzheng Gengbin Zheng], [[Mathematician#LaxKale|Laxmikant Kale]] ('''2011'''). ''Distributed Memory Load Balancing''. [http://www.springer.com/computer/swe/book/978-0-387-09765-7 Encyclopedia of Parallel Computing], [https://en.wikipedia.org/wiki/Springer_Science%2BBusiness_Media Springer]
* [https://en.wikipedia.org/wiki/George_Church George Church], [http://www.bme.jhu.edu/people/primary.php?id=1045 Yuan Gao], [http://openwetware.org/wiki/Sriram_Kosuri Sriram Kosuri] ('''2012'''). ''[http://www.sciencemag.org/content/early/2012/08/15/science.1226355 Next-Generation Digital Information Storage in DNA]''. [https://en.wikipedia.org/wiki/Science_%28journal%29 Science] <ref>[http://www.nature.com/news/dna-data-storage-breaks-records-1.11194 DNA data storage breaks records : Nature News & Comment] by [http://www.nature.com/stemcells/about_editor.html Monya Baker], August 16, 2012</ref> <ref>[http://www.talkchess.com/forum/viewtopic.php?t=44826 DNA data storage breaks records] by Terry McCracken, [[CCC]], August 18, 2012</ref>
==[[Cognition]]==
===1960 ...===
* [[Adriaan de Groot]] ('''1966'''). ''Perception and Memory versus Thought: Some Old Ideas and Recent Findings''. Problem Solving: Research, Method, and Theory (ed. B. Kleinmuntz), pp. 19-50. John Wiley, New York.
===1970 ...===
* [[Herbert Simon]], [[Kevin J. Gilmartin]] ('''1973'''). ''A Simulation of Memory for Chess Positions''. Cognitive Psychology, Vol. 5, pp. 29-46. [http://www.cs.wright.edu/~snarayan/isis/pdf/group5one.pdf pdf] » [[MAPP]]
* [[Peter W. Frey]], [[Peter Adesman]] ('''1976'''). ''[http://link.springer.com/article/10.3758%2FBF03213216?LI=true#page-1 Recall Memory for Visually Presented Chess Positions]''. [http://www.springer.com/psychology/cognitive+psychology/journal/13421 Memory & Cognition], Vol. 4, No. 5, 541-547
* [[Neil Charness]] ('''1976'''). ''[http://psycnet.apa.org/journals/xlm/2/6/641/ Memory for Chess Positions: Resistance to Interference]''. Journal of Experimental Psychology: Human Learning and Memory, Vol. 2, No. 6, pp. 641-653 » [[MAPP]]
* [[Judith Spencer Olson|Judith S. Reitman]] ('''1976'''). ''[http://deepblue.lib.umich.edu/handle/2027.42/33676 Mechanisms of Forgetting in Short-term Memory]''. [http://www.journals.elsevier.com/cognitive-psychology/ Cognitive Psychology], Vol. 2, No. 2
* [[Judith Spencer Olson|Judith S. Reitman]] ('''1976'''). ''[http://deepblue.lib.umich.edu/handle/2027.42/21741 Skilled Perception in Go: Deducing Memory Structures from Inter-Response Times]''. [http://www.journals.elsevier.com/cognitive-psychology/ Cognitive Psychology], Vol. 8, No, 3
* [[Sarah E. Goldin]] ('''1978'''). ''[http://psycnet.apa.org/journals/xlm/4/6/605/ Memory for the ordinary: Typicality effects in chess memory]''. Journal of Experimental Psychology: Human Learning and Memory, Vol. 4, No. 6, pp. 605-616
* [[Sarah E. Goldin]] ('''1979'''). ''[http://www.jstor.org/discover/10.2307/1421476?uid=3737864&uid=2129&uid=2&uid=70&uid=4&sid=21101400527007 Recognition memory for chess positions: Some preliminary research]''. [https://en.wikipedia.org/wiki/American_Journal_of_Psychology American Journal of Psychology], Vol 92, No. 1, pp. 19-32
===1980 ...===
* [[Marvin Minsky]] ('''1980'''). ''K-Lines: A Theory of Memory''. Cognitive Science 4, 117-133, [http://csjarchive.cogsci.rpi.edu/1980v04/i02/p0117p0133/MAIN.PDF pdf] <ref>[https://en.wikipedia.org/wiki/K-line_%28artificial_intelligence%29 K-line (artificial intelligence) from Wikipedia]</ref>
* [[Dennis H. Holding]], [[Robert I. Reynolds]] ('''1982'''). ''[http://link.springer.com/article/10.3758%2FBF03197635?LI=true#page-1 Recall or Evaluation of Chess Positions as Determinants of Chess Skill]''. [http://www.springer.com/psychology/cognitive+psychology/journal/13421 Memory & Cognition], Vol. 10, No. 3, 237-242
* [[A. Harry Klopf]] ('''1982'''). ''The Hedonistic Neuron: A Theory of Memory, Learning, and Intelligence''. Hemisphere Publishing Corporation, [[University of Michigan]]
===1990 ...===
* [[Fernand Gobet]] ('''1993'''). ''[http://people.brunel.ac.uk/%7Ehsstffg/papers/ModelChessMem/Chess%20Memory.html A Computer Model of Chess Memory].'' Proceedings of the 15th Annual Meeting of the Cognitive Science Society, pp. 463-468.
* [[Fernand Gobet]], [[Peter Jansen]] ('''1994'''). ''Towards a chess program based on a model of human memory.'' [[Advances in Computer Chess 7]]. [http://people.brunel.ac.uk/%7Ehsstffg/abstracts/chess_program.html abstract]
* [[Robert W. Howard]] ('''1995'''). ''Learning and Memory: Major Ideas, Principles, Issues and Applications''. Praeger, [http://www.amazon.com/Learning-Memory-Principles-Issues-Applications/dp/027594641X/ref=la_B001HPC7VM_1_1?ie=UTF8&qid=1352388827 amazon.com]
* [[Adriaan de Groot]], [[Fernand Gobet]] ('''1996'''). ''[http://people.brunel.ac.uk/%7Ehsstffg/abstracts/deGroot_abstract.html Perception and memory in chess]. Heuristics of the professional eye.'' Assen: Van Gorcum, The Netherlands. ISBN 90-232-2949-5. Chapter 9; A discussion: Two authors, two different views? [http://people.brunel.ac.uk/%7Ehsstffg/preprints/DeGroot_Gobet_Chapter_9.doc word reprint]
* [[Fernand Gobet]], [[Herbert Simon]] ('''1996'''). ''Templates in Chess Memory: A Mechanism for Recalling Several Boards.'' Cognitive Psychology, Vol. 31, pp. 1-40.
* [[Fernand Gobet]], [[Herbert Simon]] ('''1996'''). ''Recall of random and distorted positions: Implications for the theory of expertise.'' Memory & Cognition, 24, 493-503.
* [[Fernand Gobet]], [[Herbert Simon]] ('''1996'''). ''Recall of rapidly presented random chess positions is a function of skill.'' Psychonomic Bulletin & Review, 3, 159-163, [http://people.brunel.ac.uk/%7Ehsstffg/preprints/Recall_random_pos.doc word reprint]
* [[Fernand Gobet]], [[Herbert Simon]] ('''1998'''). ''Expert chess memory: Revisiting the chunking hypothesis.'' Memory, 6, 225-255
* [[Richard S. Schultetus]], [[Neil Charness]] ('''1999'''). ''Recall vs. position evaluation revisited: The importance of position-specific memory in chess skill''. [https://en.wikipedia.org/wiki/American_Journal_of_Psychology American Journal of Psychology], Vol. 112, No. 4, 555-569.
===2000 ...===
* [[Pertti Saariluoma]], [[Tei Laine]] ('''2001'''). ''[http://onlinelibrary.wiley.com/doi/10.1111/1467-9450.00223/abstract Novice construction of chess memory]''. [http://psychology.wikia.com/wiki/Scandinavian_Journal_of_Psychology Scandinavian Journal of Psychology], Vol. 42, No. 2 <ref>[[Fernand Gobet]] ('''2007'''). ''Chunk hierarchies and retrieval structures: Comments on Saariluoma and Laine. Scandinavian Journal of Psychology, 42''. [http://dspace.brunel.ac.uk/bitstream/2438/806/1/Saariluoma_Laine_reply.pdf pdf]</ref>
* [[Dharshan Kumaran]], [https://en.wikipedia.org/wiki/Eleanor_Maguire Eleanor A. Maguire] ('''2005'''). ''[http://www.jneurosci.org/content/25/31/7254.short The Human Hippocampus: Cognitive Maps or Relational Memory]?'' [https://en.wikipedia.org/wiki/The_Journal_of_Neuroscience Journal of Neuroscience], Vol. 25, No. 31
* [[Guillermo Campitelli]], [[Fernand Gobet]], Amanda Parker ('''2005'''). ''Structure and Stimulus Familiarity: A Study of Memory in Chess-Players with Functional Magnetic Resonance Imaging''. The Spanish Journal of Psychology Vol. 8, No. 2, 238-245. [http://www.estudiodepsicologia.com.ar/articles/4.pdf pdf]
* [[Alan H. Bond]] ('''2005'''). ''Representing episodic memory in a system-level model of the brain''. [http://www.elsevier.com/wps/find/journaldescription.cws_home/505628/description#description Neurocomputing], vol 65-66, pp. 261-273, [http://www.exso.com/cns04/cns04b_pub.pdf pdf]
* [[Guillermo Campitelli]], [[Fernand Gobet]], [http://www.nottingham.ac.uk/neuroscience/contact/a-z/G-L/head_kay.phtml Kay Head], [http://www.neuroscience.ox.ac.uk/directory/mark-buckley Mark Buckley], Amanda Parker ('''2007'''). ''Brain localisation of memory chunks in chessplayers.'' International Journal of Neuroscience, 117
* [[Dharshan Kumaran]] ('''2008'''). ''Short-Term Memory and The Human Hippocampus''. [https://en.wikipedia.org/wiki/The_Journal_of_Neuroscience Journal of Neuroscience], Vol. 28, No. 15, [https://drive.google.com/file/d/0B-Nvsz4idhaeUU9vVEV5QkpXZlk/view pdf]
* [[Demis Hassabis]] ('''2009'''). ''The Neural Processes Underpinning Episodic Memory''. Ph.D. thesis, [https://en.wikipedia.org/wiki/University_College_London University College London], Supervisor [https://en.wikipedia.org/wiki/Eleanor_Maguire Eleanor A. Maguire], [http://static1.1.sqspcdn.com/static/f/1096238/22752296/1369317078327/DemisHassabisThesis.pdf pdf]
=Forum Posts=
==1995 ...==
* [http://groups.google.com/group/rec.games.chess.computer/browse_frm/thread/dd8e54508bef37dd/ cache sizes] by [[Tom Kerrigan]], [[Computer Chess Forums|rgcc]], August 12, 1997
==2000 ...==
* [https://www.stmintz.com/ccc/index.php?id=293626 Difference in chess between DDR and PC133 SDRAM?] by [[Javier Ros Padilla]], [[CCC]], April 16, 2003
* [https://www.stmintz.com/ccc/index.php?id=306858 Another memory latency test] by [[Dieter Bürssner]], [[CCC]], July 17, 2003
* [http://groups.google.com/group/comp.lang.asm.x86/msg/26c662942c961ecd Re: Static memory allocation] by [[Matt Taylor]], [http://groups.google.com/group/comp.lang.asm.x86/topics comp.lang.asm.x86], July 03, 2004
==2005 ...==
* [http://www.talkchess.com/forum/viewtopic.php?t=21233 Minimizing Sharing of Data between Physical Processors] by [[Pradu Kannan]], [[CCC]], May 19, 2008
* [http://www.talkchess.com/forum/viewtopic.php?t=27229 malloc more than 2GB ?] by [[Frank Phillips]], [[CCC]], March 28, 2009
* [http://www.talkchess.com/forum/viewtopic.php?topic_view=threads&p=285407 Cache pollution when reading/writing hash table] by [[Marco Costalba]], [[CCC]], August 09, 2009
* [http://www.talkchess.com/forum/viewtopic.php?t=29434 Questions on volatile keyword and memory barriers] by [[Pradu Kannan]], [[CCC]], August 16, 2009
==2010 ...==
* [http://www.talkchess.com/forum/viewtopic.php?t=36516 Is a querying the hash tables such a huge bottleneck?] by [[Oliver Uwira]], [[CCC]], October 28, 2010
'''2011'''
* [http://www.talkchess.com/forum/viewtopic.php?t=38441 MSVC calloc question] by [[Harm Geert Muller]], [[CCC]], March 17, 2011
'''2012'''
* [http://www.talkchess.com/forum/viewtopic.php?t=44826 DNA data storage breaks records] by Terry McCracken, [[CCC]], August 18, 2012 <ref>[https://en.wikipedia.org/wiki/George_Church George Church], [http://www.bme.jhu.edu/people/primary.php?id=1045 Yuan Gao], [http://openwetware.org/wiki/Sriram_Kosuri Sriram Kosuri] ('''2012'''). ''[http://www.sciencemag.org/content/early/2012/08/15/science.1226355 Next-Generation Digital Information Storage in DNA]''. [https://en.wikipedia.org/wiki/Science_%28journal%29 Science]</ref>
'''2013'''
* [http://www.talkchess.com/forum/viewtopic.php?t=46968 DrMemory: memory debugger tool for Windows (and Linux)] by [[Martin Sedlak]], [[CCC]], January 22, 2013 » [[Debugging]]
* [http://www.open-chess.org/viewtopic.php?f=5&t=2262 Multi-threaded memory access] by [[Vadim Demichev|ThinkingALot]], [[Computer Chess Forums|OpenChess Forum]], February 10, 2013 » [[Thread]], [[Shared Hash Table]]
* [http://www.talkchess.com/forum/viewtopic.php?t=47706 Hybrid Memory Cube effect on computer chess] by [[Albert Silver]], [[CCC]], April 05, 2013 <ref>[https://en.wikipedia.org/wiki/Hybrid_Memory_Cube Hybrid Memory Cube from Wikipedia]</ref>
* [http://www.talkchess.com/forum/viewtopic.php?t=49388 MEM_LARGE_PAGES] by [[Alvaro Cardoso]], [[CCC]], September 18, 2013
* [http://www.talkchess.com/forum/viewtopic.php?t=49592 Multithreaded LRU] by [[Alvaro Cardoso]], [[CCC]], October 06, 2013 » [[Endgame Tablebases]]
* [http://www.talkchess.com/forum/viewtopic.php?t=49702 tablebase caching / mmap() / page cache] by [[Ronald de Man]], [[CCC]], October 13, 2013 » [[Endgame Tablebases]], [[Syzygy Bases]]
* [http://www.talkchess.com/forum/viewtopic.php?t=50334 Table Base Cache Size question] by Rob Nicholas, [[CCC]], December 05, 2013 » [[Endgame Tablebases]]
'''2014'''
* [http://www.talkchess.com/forum/viewtopic.php?t=51087 Intel i3 L2 cache] by [[Harm Geert Muller]], [[CCC]], January 28, 2014 » [[x86-64]] <ref>[https://en.wikipedia.org/wiki/Intel_Core#Core_i3 Intel Nehalem Core i3]</ref>
* [http://www.talkchess.com/forum/viewtopic.php?t=51824 c++11 std::atomic and memory_order_relaxed] by Kevin Hearn, [[CCC]], April 01, 2014 » [[Cpp|C++]]
* [http://www.talkchess.com/forum/viewtopic.php?t=53849 Speculative prefetch] by [[Peter Österlund]], [[CCC]], September 27, 2014 » [[Transposition Table]]
* [http://www.talkchess.com/forum/viewtopic.php?t=54064 Tablebase access using a Solid State Disk] by [[Steven Edwards]], [[CCC]], October 16, 2014 » [[Endgame Tablebases]]
* [http://www.talkchess.com/forum/viewtopic.php?t=54636 USB 3 Storage for Syzygy WDL files] by [[Louis Zulli]], [[CCC]], December 13, 2014 » [[Syzygy Bases]], [[Memory#USB3|USB 3.0]]
==2015 ...==
* [http://www.talkchess.com/forum/viewtopic.php?t=55132 Low-RAM engine] by [[Harm Geert Muller]], [[CCC]], January 28, 2015
* [http://www.talkchess.com/forum/viewtopic.php?t=55516 The effect of dual channel RAM] by [[Volker Annuss]], [[CCC]], March 01, 2015 » [[Arminius]]
* [http://www.talkchess.com/forum/viewtopic.php?t=56856 One hundred thirty gigabytes] by [[Steven Edwards]], [[CCC]], July 03, 2015
* [http://www.talkchess.com/forum/viewtopic.php?t=57149 3D XPoint] by [[Edmund Moshammer]], [[CCC]], August 02, 2015 <ref>[https://en.wikipedia.org/wiki/3D_XPoint 3D XPoint from Wikipedia]</ref>
* [http://www.talkchess.com/forum/viewtopic.php?t=57924 Hash cache] by [[Harm Geert Muller]], [[CCC]], October 12, 2015 » [[Hash Table]], [[Transposition Table]]
'''2016'''
* [http://www.talkchess.com/forum/viewtopic.php?t=58830 NUMA 101] by [[Robert Hyatt]], [[CCC]], January 07, 2016 » [[Parallel Search]]
* [http://www.talkchess.com/forum/viewtopic.php?t=60875 NUMA in a YBWC implementation] by [[Edsel Apostol]], [[CCC]], July 20, 2016 » [[Young Brothers Wait Concept]]
* [https://groups.google.com/d/msg/fishcooking/ezt6MrAuXqs/qIR2HEciEgAJ lets get the ball moving down the field on numa awareness] by [[Mohammed Li]], [[Computer Chess Forums|FishCooking]], August 30, 2016 » [[NUMA]], [[Stockfish]], [[asmFish]]
* [http://www.talkchess.com/forum/viewtopic.php?t=61423 Tipical cache and branch misses for a chess engine] by [[Nicu Ionita]], [[CCC]], September 14, 2016 » [[Avoiding Branches]], [[Profiling]]
* [http://www.talkchess.com/forum/viewtopic.php?t=61472 What do you do with NUMA?] by [[Matthew Lai]], [[CCC]], September 19, 2016 » [[NUMA]]
* [http://rybkaforum.net/cgi-bin/rybkaforum/topic_show.pl?tid=31867 L3 cache, RAM and other performance factors] by Nimzy, [[Computer Chess Forums|Rybka Forum]], December 04, 2016 » [[Playing Strength]]
'''2017'''
* [http://www.talkchess.com/forum/viewtopic.php?t=63652 6-men Syzygy from HDD and USB 3.0] by [[Kai Laskos]], [[CCC]], April 04, 2017 » [[Komodo]], [[Playing Strength]], [[Syzygy Bases]], [[Memory#USB3|USB 3.0]]
* [http://www.talkchess.com/forum/viewtopic.php?t=63886 RAM speed and engine strength] by John Hartmann, [[CCC]], May 03, 2017 » [[Memory#RAM|RAM]], [[Playing Strength]]
* [http://www.talkchess.com/forum/viewtopic.php?t=65284 Probing tablebases through USB 3.0] by [[Jon Fredrik Åsvang]], [[CCC]], September 25, 2017 » , [[Syzygy Bases]], [[Memory#USB3|USB 3.0]]
=External Links=
* [https://en.wikipedia.org/wiki/Memory_%28disambiguation%29 Memory (disambiguation) from Wikipedia]
==Computer Memory==
* [http://ljkrakauer.com/LJK/essays/bits.htm Bits] by [[Lawrence J. Krakauer]]
* [https://en.wikipedia.org/wiki/Computer_memory Computer memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Data_dictionary Data dictionary from Wikipedia]
* [https://en.wikipedia.org/wiki/Lookup_table Lookup table from Wikipedia]
* [http://ljkrakauer.com/LJK/60s/moby.htm Moby Memory] by [[Lawrence J. Krakauer]] » [[PDP-6]]
* [https://en.wikipedia.org/wiki/Multi-level_Cell Multi-level cell from Wikipedia]
* <span id="Semiconductor"></span>[https://en.wikipedia.org/wiki/Semiconductor_memory Semiconductor memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Universal_memory Universal memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Von_Neumann_architecture Von Neumann architecture from Wikipedia]
==Gustavo Duarte's Blog==
from [http://duartes.org/gustavo/blog/best-of Best Of] by [http://duartes.org/gustavo/blog/ Gustavo Duarte]:
* [http://duartes.org/gustavo/blog/post/motherboard-chipsets-memory-map Motherboard Chipsets and the Memory Map]
* [http://duartes.org/gustavo/blog/post/anatomy-of-a-program-in-memory Anatomy of a Program in Memory]
* [http://duartes.org/gustavo/blog/post/how-the-kernel-manages-your-memory How The Kernel Manages Your Memory]
* [http://duartes.org/gustavo/blog/post/page-cache-the-affair-between-memory-and-files Page Cache, the Affair Between Memory and Files]
* [http://duartes.org/gustavo/blog/post/memory-translation-and-segmentation Memory Translation and Segmentation]
* [http://duartes.org/gustavo/blog/post/getting-physical-with-memory Getting Physical With Memory]
* [http://duartes.org/gustavo/blog/post/cpu-rings-privilege-and-protection CPU Rings, Privilege, and Protection]
* [http://duartes.org/gustavo/blog/post/intel-cpu-caches Cache: a place for concealment and safekeeping]
* [http://duartes.org/gustavo/blog/post/the-thing-king The Thing King]
==[[Cognition]]==
* [https://en.wikipedia.org/wiki/Cognition Cognition from Wikipedia]
* [http://en.wikibooks.org/wiki/Cognitive_Psychology_and_Cognitive_Neuroscience/Memory Cognitive Psychology and Cognitive Neuroscience/Memory from Wikibooks]
* [https://en.wikipedia.org/wiki/Long-term_memory Long-term memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Memory Memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Recall_%28memory%29 Recall (memory) from Wikipedia]
* [https://en.wikipedia.org/wiki/Short-term_memory Short-term memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Working_memory Working memory from Wikipedia]
==Neuroscience==
* [https://en.wikipedia.org/wiki/Neuroscience Neuroscience from Wikipedia]
* [https://en.wikipedia.org/wiki/Biological_neural_network Biological neural network from Wikipedia]
* [https://en.wikipedia.org/wiki/Brain Brain from Wikipedia]
* [https://en.wikipedia.org/wiki/Cognitive_neuroscience Cognitive neuroscience from Wikipedia]
* [http://www.fourmilab.ch/documents/comp_mem_nat_life/ Computation, Memory, Nature, and Life] - Is digital storage the secret of life? by [https://en.wikipedia.org/wiki/John_Walker_%28programmer%29 John Walker]
* [https://en.wikipedia.org/wiki/Human_brain Human brain from Wikipedia]
* [http://en.wikiversity.org/wiki/Memory_%28biological%29 Memory (biological)] from [http://en.wikiversity.org/wiki/Wikiversity:Main_Page Wikiversity]
==Misc==
* [https://en.wikipedia.org/wiki/Art_of_memory Art of memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Electric_Fence Electric Fence (Memory Debugger) from Wikipedia] » [[Debugging]]
* [https://en.wikipedia.org/wiki/Mnemonic Mnemonic from Wikipedia]
* [https://en.wikipedia.org/wiki/Moore%27s_law Moore's law from Wikipedia]
* [https://en.wikipedia.org/wiki/Paper_data_storage Paper data storage from Wikipedia]
* [[Videos#AlDiMeola|Al Di Meola]], [[Videos#StanleyClarke|Stanley Clarke]], [[Videos#JeanLucPonty|Jean luc Ponty]] - [https://en.wikipedia.org/wiki/The_Rite_of_Strings Memory Canyon], [https://en.wikipedia.org/wiki/Montreux_Jazz_Festival Montreux] 1994, [https://en.wikipedia.org/wiki/YouTube YouTube] Video
: {{#evu:https://www.youtube.com/watch?v=bRe0IhgJ2W8|alignment=left|valignment=top}}
=References=
<references />
'''[[Hardware|Up one Level]]'''
