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'''[[Main Page|Home]] * [[Hardware]] * Itanium'''
[[FILE:Intel-Itanium-Processor-9500.jpg|border|right|thumb|link=http://wccftech.com/intel-itanium-kittson-ia64-processors-32nm/| Die shot of [https://en.wikipedia.org/wiki/List_of_Intel_Itanium_microprocessors#Poulson_.2832_nm.29 Itanium 9500] <ref>[http://wccftech.com/intel-itanium-kittson-ia64-processors-32nm/ Intel's Next Generation Itanium 'Kittson' IA64 Processor Detailed - 32nm Process, 9300/9500 Socket Compatible] by [http://wccftech.com/author/usmanpirzada/ Usman Pirzada], April 2015</ref> ]]
'''Itanium''',<br/>
a family of 64-bit microprocessors by [[Intel]] that implement the [https://en.wikipedia.org/wiki/IA-64 IA-64] architecture originated by [https://en.wikipedia.org/wiki/Hewlett-Packard Hewlett-Packard] (HP) and later jointly developed by HP and Intel. While the early development started in 1989 by HP, Intel officially announced the name of the processor, Itanium, on October 4, 1999 <ref>[https://archive.is/IUNih Intel names Merced chip Itanium - CNET News] by [https://www.linkedin.com/pub/michael-kanellos/0/803/20b Michael Kanellos], [https://en.wikipedia.org/wiki/CNET CNET News], October 4, 1999</ref>. The Itanium [https://en.wikipedia.org/wiki/List_of_Intel_Itanium_microprocessors#.22Merced.22_.28180_nm.29 Merced] was released on June 2001, [https://en.wikipedia.org/wiki/Itanium#Itanium_2:_2002.E2.80.932010 Itanium 2] McKinley and Madison in 2002 and 2003 respectively, the so far most recent [https://en.wikipedia.org/wiki/List_of_Intel_Itanium_microprocessors#Poulson_.2832_nm.29 Poulson] (Itanium 9500) in November 2012, and [https://en.wikipedia.org/wiki/Itanium#Kittson Kittson] planned for 2015 <ref>[https://en.wikipedia.org/wiki/Itanium Itanium from Wikipedia]</ref>. Initially intended as Intel's successor for [[x86]] aka IA-32 architecture, [[AMD]] forced Intel to change priorities with [[x86-64]].
=Architecture=
IA-64 applies [https://en.wikipedia.org/wiki/Explicitly_parallel_instruction_computing explicitly parallel instruction computing] (EPIC) which allows the processor to execute multiple instructions in each clock cycle. EPIC implements a form of [https://en.wikipedia.org/wiki/Very_long_instruction_word very long instruction word] (VLIW) architecture, in which a single instruction word contains up to three instructions. With EPIC, the compiler determines in advance which instructions can be executed at the same time, rather than the processor itself. The architecture implements [https://en.wikipedia.org/wiki/Branch_predication branch predication] and [https://en.wikipedia.org/wiki/Speculative_execution speculation], has 128 64-bit general purpose registers, 128 82-bit floating point or [[SIMD and SWAR Techniques|SIMD]] registers, 64 one-bit predicates, and eight branch registers, and thirty functional execution units in eleven groups, such as various [[Combinatorial Logic#ALU|ALUs]], [[SIMD and SWAR Techniques|SIMD]] units with parallel shift and multiply, and [[Population Count|population count]] unit.
[[FILE:Itanium architecture.svg|none|border|text-bottom]]
Itanium architecture <ref>Diagram of the architecture of the Itanium (IA-64) 64-bit Intel microprocessor, Image by [https://commons.wikimedia.org/wiki/User:Fred_the_Oyster Fred the Oyster], September 08, 2014, [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons], [https://en.wikipedia.org/wiki/IA-64 IA-64 from Wikipedia], [https://creativecommons.org/licenses/by-sa/4.0/deed.en CC BY-SA 4.0]</ref>
=x86 Support=
[[x86]] (IA-32) instructions were supported by hardware <ref>[https://www.stmintz.com/ccc/index.php?id=277735 Re: Deep-Fritz 18 on a 64 cpu itanium (intel not AMD) system] by [[Eugene Nalimov]], [[CCC]], January 16, 2003</ref> , and since 2006 emulated with the [https://en.wikipedia.org/wiki/IA-32_Execution_Layer IA-32 Execution Layer].
=Chess Programs=
[[TSCP]] <ref>[https://www.stmintz.com/ccc/index.php?id=334348 Re: Question: Itanium Info] by K. Burcham, [[CCC]], December 08, 2003</ref> , [[Tinker]] <ref>[https://www.stmintz.com/ccc/index.php?id=284689 Itanium2 Testing Crafty & Tinker Informal Results] by [[Brian Richardson]], [[CCC]], February 16, 2003</ref> and [[Crafty]] were mentioned running under Itanium. While the original Merced was disappointing, [[Robert Hyatt]] reported a good performance of Crafty on McKinley in 2003 <ref>[https://www.stmintz.com/ccc/index.php?id=334474 Re: Question: Itanium Info] by [[Robert Hyatt]], [[CCC]], December 09, 2003</ref> , close to the [[x86-64|Opteron]] with double frequency. [[Eugene Nalimov]], at that time member of the [[Microsoft]] Visual compiler team targeting the Itanium platform, provided a IA-64 optimzed [[BitScan]] aka firstOne and lastOne in [[C]] <ref>[https://www.stmintz.com/ccc/index.php?id=124712 Re: Will the Itanium have a BSF or BSR instruction?] by [[Eugene Nalimov]], [[CCC]], August 16, 2000</ref> , taking advantage of IA-64's [https://en.wikipedia.org/wiki/Branch_predication branch predication].
=See also=
* [[i860]]
* [[x86]]
* [[x86-64]]
=Forum Posts=
* [https://www.stmintz.com/ccc/index.php?id=116773 Re: What are the chances of getting a new 64bit instruction for chess :)] by [[Eugene Nalimov]], [[CCC]], June 27, 2000
* [https://www.stmintz.com/ccc/index.php?id=124638 Will the Itanium have a BSF or BSR instruction?] by Larry Griffiths, [[CCC]], August 15, 2000 » [[BitScan]]
* [https://www.stmintz.com/ccc/index.php?id=150518 Itanium] by John Dahlem, [[CCC]], January 17, 2001
* [https://www.stmintz.com/ccc/index.php?id=232633 Intel Itanium 2 Benchmarks] by [[Vincent Lejeune]], [[CCC]], May 29, 2002
* [https://www.stmintz.com/ccc/index.php?id=284689 Itanium2 Testing Crafty & Tinker Informal Results] by [[Brian Richardson]], [[CCC]], February 16, 2003
* [https://www.stmintz.com/ccc/index.php?id=283740 IA-64 vs OOOE (attn Taylor, Hyatt)] by [[Tom Kerrigan]], [[CCC]], February 11, 2003
* [https://www.stmintz.com/ccc/index.php?id=334345 Question: Itanium Info] by Slater Wold, [[CCC]], December 08, 2003
=External Links=
* [http://www.intel.com/content/www/us/en/processors/itanium/itanium-processor.html Intel® Itanium® Processors]
* [https://en.wikipedia.org/wiki/Itanium Itanium from Wikipedia]
* [https://en.wikipedia.org/wiki/IA-64 IA-64 from Wikipedia]
* [https://en.wikipedia.org/wiki/List_of_Intel_Itanium_microprocessors List of Intel Itanium microprocessors from Wikipedia]
* [http://www.pcmag.com/article.aspx/curl/2339629 How the Itanium Killed the Computer Industry] by [http://www.pcmag.com/author-bio/john-c.-dvorak John C. Dvorak], [https://en.wikipedia.org/wiki/PC_Magazine PCMag.com], January 26, 2009
* [http://wccftech.com/intel-itanium-kittson-ia64-processors-32nm/ Intel's Next Generation Itanium 'Kittson' IA64 Processor Detailed - 32nm Process, 9300/9500 Socket Compatible] by [http://wccftech.com/author/usmanpirzada/ Usman Pirzada], April 2015
=References=
<references />
'''[[Hardware|Up one Level]]'''
[[Category:Die]]
[[FILE:Intel-Itanium-Processor-9500.jpg|border|right|thumb|link=http://wccftech.com/intel-itanium-kittson-ia64-processors-32nm/| Die shot of [https://en.wikipedia.org/wiki/List_of_Intel_Itanium_microprocessors#Poulson_.2832_nm.29 Itanium 9500] <ref>[http://wccftech.com/intel-itanium-kittson-ia64-processors-32nm/ Intel's Next Generation Itanium 'Kittson' IA64 Processor Detailed - 32nm Process, 9300/9500 Socket Compatible] by [http://wccftech.com/author/usmanpirzada/ Usman Pirzada], April 2015</ref> ]]
'''Itanium''',<br/>
a family of 64-bit microprocessors by [[Intel]] that implement the [https://en.wikipedia.org/wiki/IA-64 IA-64] architecture originated by [https://en.wikipedia.org/wiki/Hewlett-Packard Hewlett-Packard] (HP) and later jointly developed by HP and Intel. While the early development started in 1989 by HP, Intel officially announced the name of the processor, Itanium, on October 4, 1999 <ref>[https://archive.is/IUNih Intel names Merced chip Itanium - CNET News] by [https://www.linkedin.com/pub/michael-kanellos/0/803/20b Michael Kanellos], [https://en.wikipedia.org/wiki/CNET CNET News], October 4, 1999</ref>. The Itanium [https://en.wikipedia.org/wiki/List_of_Intel_Itanium_microprocessors#.22Merced.22_.28180_nm.29 Merced] was released on June 2001, [https://en.wikipedia.org/wiki/Itanium#Itanium_2:_2002.E2.80.932010 Itanium 2] McKinley and Madison in 2002 and 2003 respectively, the so far most recent [https://en.wikipedia.org/wiki/List_of_Intel_Itanium_microprocessors#Poulson_.2832_nm.29 Poulson] (Itanium 9500) in November 2012, and [https://en.wikipedia.org/wiki/Itanium#Kittson Kittson] planned for 2015 <ref>[https://en.wikipedia.org/wiki/Itanium Itanium from Wikipedia]</ref>. Initially intended as Intel's successor for [[x86]] aka IA-32 architecture, [[AMD]] forced Intel to change priorities with [[x86-64]].
=Architecture=
IA-64 applies [https://en.wikipedia.org/wiki/Explicitly_parallel_instruction_computing explicitly parallel instruction computing] (EPIC) which allows the processor to execute multiple instructions in each clock cycle. EPIC implements a form of [https://en.wikipedia.org/wiki/Very_long_instruction_word very long instruction word] (VLIW) architecture, in which a single instruction word contains up to three instructions. With EPIC, the compiler determines in advance which instructions can be executed at the same time, rather than the processor itself. The architecture implements [https://en.wikipedia.org/wiki/Branch_predication branch predication] and [https://en.wikipedia.org/wiki/Speculative_execution speculation], has 128 64-bit general purpose registers, 128 82-bit floating point or [[SIMD and SWAR Techniques|SIMD]] registers, 64 one-bit predicates, and eight branch registers, and thirty functional execution units in eleven groups, such as various [[Combinatorial Logic#ALU|ALUs]], [[SIMD and SWAR Techniques|SIMD]] units with parallel shift and multiply, and [[Population Count|population count]] unit.
[[FILE:Itanium architecture.svg|none|border|text-bottom]]
Itanium architecture <ref>Diagram of the architecture of the Itanium (IA-64) 64-bit Intel microprocessor, Image by [https://commons.wikimedia.org/wiki/User:Fred_the_Oyster Fred the Oyster], September 08, 2014, [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons], [https://en.wikipedia.org/wiki/IA-64 IA-64 from Wikipedia], [https://creativecommons.org/licenses/by-sa/4.0/deed.en CC BY-SA 4.0]</ref>
=x86 Support=
[[x86]] (IA-32) instructions were supported by hardware <ref>[https://www.stmintz.com/ccc/index.php?id=277735 Re: Deep-Fritz 18 on a 64 cpu itanium (intel not AMD) system] by [[Eugene Nalimov]], [[CCC]], January 16, 2003</ref> , and since 2006 emulated with the [https://en.wikipedia.org/wiki/IA-32_Execution_Layer IA-32 Execution Layer].
=Chess Programs=
[[TSCP]] <ref>[https://www.stmintz.com/ccc/index.php?id=334348 Re: Question: Itanium Info] by K. Burcham, [[CCC]], December 08, 2003</ref> , [[Tinker]] <ref>[https://www.stmintz.com/ccc/index.php?id=284689 Itanium2 Testing Crafty & Tinker Informal Results] by [[Brian Richardson]], [[CCC]], February 16, 2003</ref> and [[Crafty]] were mentioned running under Itanium. While the original Merced was disappointing, [[Robert Hyatt]] reported a good performance of Crafty on McKinley in 2003 <ref>[https://www.stmintz.com/ccc/index.php?id=334474 Re: Question: Itanium Info] by [[Robert Hyatt]], [[CCC]], December 09, 2003</ref> , close to the [[x86-64|Opteron]] with double frequency. [[Eugene Nalimov]], at that time member of the [[Microsoft]] Visual compiler team targeting the Itanium platform, provided a IA-64 optimzed [[BitScan]] aka firstOne and lastOne in [[C]] <ref>[https://www.stmintz.com/ccc/index.php?id=124712 Re: Will the Itanium have a BSF or BSR instruction?] by [[Eugene Nalimov]], [[CCC]], August 16, 2000</ref> , taking advantage of IA-64's [https://en.wikipedia.org/wiki/Branch_predication branch predication].
=See also=
* [[i860]]
* [[x86]]
* [[x86-64]]
=Forum Posts=
* [https://www.stmintz.com/ccc/index.php?id=116773 Re: What are the chances of getting a new 64bit instruction for chess :)] by [[Eugene Nalimov]], [[CCC]], June 27, 2000
* [https://www.stmintz.com/ccc/index.php?id=124638 Will the Itanium have a BSF or BSR instruction?] by Larry Griffiths, [[CCC]], August 15, 2000 » [[BitScan]]
* [https://www.stmintz.com/ccc/index.php?id=150518 Itanium] by John Dahlem, [[CCC]], January 17, 2001
* [https://www.stmintz.com/ccc/index.php?id=232633 Intel Itanium 2 Benchmarks] by [[Vincent Lejeune]], [[CCC]], May 29, 2002
* [https://www.stmintz.com/ccc/index.php?id=284689 Itanium2 Testing Crafty & Tinker Informal Results] by [[Brian Richardson]], [[CCC]], February 16, 2003
* [https://www.stmintz.com/ccc/index.php?id=283740 IA-64 vs OOOE (attn Taylor, Hyatt)] by [[Tom Kerrigan]], [[CCC]], February 11, 2003
* [https://www.stmintz.com/ccc/index.php?id=334345 Question: Itanium Info] by Slater Wold, [[CCC]], December 08, 2003
=External Links=
* [http://www.intel.com/content/www/us/en/processors/itanium/itanium-processor.html Intel® Itanium® Processors]
* [https://en.wikipedia.org/wiki/Itanium Itanium from Wikipedia]
* [https://en.wikipedia.org/wiki/IA-64 IA-64 from Wikipedia]
* [https://en.wikipedia.org/wiki/List_of_Intel_Itanium_microprocessors List of Intel Itanium microprocessors from Wikipedia]
* [http://www.pcmag.com/article.aspx/curl/2339629 How the Itanium Killed the Computer Industry] by [http://www.pcmag.com/author-bio/john-c.-dvorak John C. Dvorak], [https://en.wikipedia.org/wiki/PC_Magazine PCMag.com], January 26, 2009
* [http://wccftech.com/intel-itanium-kittson-ia64-processors-32nm/ Intel's Next Generation Itanium 'Kittson' IA64 Processor Detailed - 32nm Process, 9300/9500 Socket Compatible] by [http://wccftech.com/author/usmanpirzada/ Usman Pirzada], April 2015
=References=
<references />
'''[[Hardware|Up one Level]]'''
[[Category:Die]]
