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[https://en.wikipedia.org/wiki/Altera Altera] FPGA <ref>[https://en.wikipedia.org/wiki/Field-programmable_gate_array from Wikipedia]</ref> ]]

a [https://en.wikipedia.org/wiki/Field-programmability field-programmable] [https://en.wikipedia.org/wiki/Integrated_circuit integrated circuit] consisting of a two-dimensional [[Array|array]] of logic blocks interconnected by a hierarchy of reconfigurable routing channels. The behavior of a FPGA is defined by a schematic design or by a [https://en.wikipedia.org/wiki/Hardware_description_language hardware description language] (HDL), most notably [https://en.wikipedia.org/wiki/VHDL VHDL] and [https://en.wikipedia.org/wiki/Verilog Verilog]. FPGA cards of their main suppliers [https://en.wikipedia.org/wiki/Xilinx Xilinx] <ref>[http://www.xilinx.com/ All Programmable Technologies from Xilinx Inc.]</ref> and [https://en.wikipedia.org/wiki/Altera Altera] <ref>[http://www.altera.com/ FPGA CPLD and ASIC from Altera]</ref> can be plugged into a [[IBM PC|PC]] with communication over the [https://en.wikipedia.org/wiki/Conventional_PCI PCI] or [https://en.wikipedia.org/wiki/PCI_Express PCI Express] bus. [[IBM|IBM's]] [https://en.wikipedia.org/wiki/POWER8 POWER8] processor, introduced in August 2013, features a CAPI port (Coherent Accelerator Processor Interface) is layered on top of [https://en.wikipedia.org/wiki/PCI_Express#PCI_Express_3.x PCI Express 3.0] suited to connect custom hardware such as FPGAs <ref>[http://wccftech.com/ibm-power8-processor-architecture-detailed/ IBM Power8 Processor Detailed - Features 22nm Design With 12 Cores, 96 MB eDRAM L3 Cache and 4 GHz Clock Speed]</ref> <ref>[http://www.talkchess.com/forum/viewtopic.php?t=54474&start=17 Re: FPGA chess] by [[Milos Stanisavljevic]], [[CCC]], November 28, 2014</ref>.