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[[FILE:Altera StratixIVGX FPGA.jpg|border|right|thumb|

a [https://en.wikipedia.org/wiki/Field-programmability field-programmable] [https://en.wikipedia.org/wiki/Integrated_circuit integrated circuit] consisting of a two-dimensional [[Array|array]] of logic blocks interconnected by a hierarchy of reconfigurable routing channels. The behavior of a FPGA is defined by a schematic design or by a [https://en.wikipedia.org/wiki/Hardware_description_language hardware description language] (HDL), most notably [https://en.wikipedia.org/wiki/VHDL VHDL] and [https://en.wikipedia.org/wiki/Verilog Verilog]. FPGA cards of their main suppliers [https://en.wikipedia.org/wiki/Xilinx Xilinx] <ref>[http://www.xilinx.com/ All Programmable Technologies from Xilinx Inc.]</ref> and [https://en.wikipedia.org/wiki/Altera Altera] <ref>[http://www.altera.com/ FPGA CPLD and ASIC from Altera]</ref> can be plugged into a [[IBM PC|PC]] with communication over the [https://en.wikipedia.org/wiki/Conventional_PCI PCI] or [https://en.wikipedia.org/wiki/PCI_Express PCI Express] bus. [[IBM|IBM's]] [https://en.wikipedia.org/wiki/POWER8 POWER8] processor, introduced in August 2013, features a CAPI port (Coherent Accelerator Processor Interface) is layered on top of [https://en.wikipedia.org/wiki/PCI_Express#PCI_Express_3.x PCI Express 3.0] suited to connect custom hardware such as FPGAs <ref>[http://wccftech.com/ibm-power8-processor-architecture-detailed/ IBM Power8 Processor Detailed - Features 22nm Design With 12 Cores, 96 MB eDRAM L3 Cache and 4 GHz Clock Speed]</ref> <ref>[http://www.talkchess.com/forum/viewtopic.php?t=54474&start=17 Re: FPGA chess] by [[Milos Stanisavljevic]], [[CCC]], November 28, 2014</ref>.

* [http://www.linkedin.com/pub/james-bowman/9/511/358 James Bowman] ('''2010'''). ''J1: a small Forth CPU Core for FPGAs''. [http://www.complang.tuwien.ac.at/anton/euroforth/ef10/ EuroForth 2010], [http://www.excamera.com/files/j1.pdf pdf] <ref>[http://www.excamera.com/sphinx/fpga-j1.html The J1 Forth CPU — excamera]</ref>

* [https://dblp.uni-trier.de/pers/hd/k/Kadric:Edin Edin Kadric], [http://my.ece.queensu.ca/people/N-Manjikian/index.html Naraig Manjikian], [[Zeljko Zilic]] ('''2012'''). ''[https://www.semanticscholar.org/paper/An-FPGA-implementation-for-a-high-speed-optical-a-Kadric-Manjikian/403966143ae4ded89f519214124761d667821a11 An FPGA implementation for a high-speed optical link with a PCIe interface]''. [https://dblp.uni-trier.de/db/conf/socc/socc2012.html SoCC 2012]

==2015 ...==

=Forum Posts=

==2000 ...==

* [https://www.stmintz.com/ccc/index.php?id=92614 Chip design project & another request for Belle/DT/DB info] by [[Tom Kerrigan]], [[CCC]], January 27, 2000 » [[Belle]], [[Deep Thought]], [[Deep Blue]]

* [https://www.stmintz.com/ccc/index.php?id=221124 A Response From Marc Boule] by [[Slater Wold]], [[CCC]], April 02, 2002

* [https://www.stmintz.com/ccc/index.php?id=251005 Re: Thesis by Marc Boule] by [[Marc Boulé]], [[CCC]], September 08, 2002

* [http://www.alpha-data.com/ Alpha Data - High Performance Computing with Xilinx Virtex-7 FPGAs]

==Misc==

: {{#evu:https://www.youtube.com/watch?v=mJbGKOmNXCs|alignment=left|valignment=top}}

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