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'''[[Main Page|Home]] * [[Hardware]] * Cray T3E'''
[[FILE:Processor board cray-2 hg.jpg|border|right|thumb| Cray T3E processor board <ref>Processor board of a CRAY T3E-136/ac (=air-cooled) massive parallel computer (operational ca. 1997-2005). The related system had 136 processors in total. This board has four Dec-Alpha EV5 processors (300 MHz) with local memory chips and router chips onboard. [[DEC Alpha|Alpha]] processors were superscalar with two floating point operations per cycle. Authors: [https://commons.wikimedia.org/wiki/User:Hgrobe Hannes Grobe] & [http://www.awi.de/People/show?wuebber Chresten Wübber], [https://en.wikipedia.org/wiki/Alfred_Wegener_Institute_for_Polar_and_Marine_Research Alfred Wegener Institute for Polar and Marine Research], [https://en.wikipedia.org/wiki/Bremerhaven Bremerhaven], Germany, August 08 2006, [https://creativecommons.org/licenses/by-sa/2.5 CC-BY-SA-2.5], [https://en.wikipedia.org/wiki/Cray_T3E Cray T3E from Wikipedia], [https://en.wikipedia.org/wiki/Alpha_21164 Alpha 21164 from Wikipedia]</ref> ]]
'''Cray T3E''',<br/>
[https://en.wikipedia.org/wiki/Cray#Cray_Research_Inc._and_Cray_Computer_Corporation:_1972_to_1996 Cray Research's] second-generation [https://en.wikipedia.org/wiki/Massively_parallel_%28computing%29 massively parallel] [https://en.wikipedia.org/wiki/Supercomputer supercomputer] architecture, launched in 1995 as successor of the [[Cray T3D|T3D]]. The T3E is a scalable [https://en.wikipedia.org/wiki/Distributed_computing distributed] [[NUMA]] architecture containing up to 2176 processing element (PE) nodes of initially 300 MHz [[DEC Alpha|DEC Alpha 21164]] processor with 64 MiB to 2 GiB of [[Memory#RAM|DRAM]] interconnected as a [https://en.wikipedia.org/wiki/Torus_interconnect 3D torus], so that each processor can access the memory of every other processor. Later models consists of faster Alpha 21164A and 21264 processors.
=Chess Programs=
* [[Zugzwang (Program)|Zugzwang]]
=See also=
* [[Cray-1]]
* [[Cray X-MP]]
* [[Cray T3D]]
=Manuals=
* [http://www.filibeto.org/~aduritz/truetrue/supercomputing/cray/datasheets/t3e.pdf Cray T3E-1350 Datasheet] (pdf)
=Publications=
* [[Rainer Feldmann]], [[Burkhard Monien]] ('''1998'''). ''Selective Game Tree Search on a Cray T3E''. [https://pdfs.semanticscholar.org/27e6/f73eb509511c20543ddae5470259077d8dfc.pdf pdf]
* [http://dblp.uni-trier.de/pers/hd/d/Dungworth:Michael Michael Dungworth], [http://dblp.uni-trier.de/pers/hc/h/Harrell:James James Harrell], [http://dblp.uni-trier.de/pers/hc/l/Levine:Michael Michael Levine], [http://dblp.uni-trier.de/pers/hc/n/Nelson:Stephen Stephen Nelson], [http://dblp.uni-trier.de/pers/hc/o/Oberlin:Steven Steven Oberlin], [http://dblp.uni-trier.de/pers/hc/r/Reinhardt:Steven_P= Steven P. Reinhardt] ('''2011'''). ''[http://link.springer.com/referenceworkentry/10.1007%2F978-0-387-09766-4_306 CRAY T3E]''. [http://link.springer.com/book/10.1007/978-0-387-09766-4 Encyclopedia of Parallel Computing], [https://en.wikipedia.org/wiki/Springer_Science%2BBusiness_Media Springer]
=External Links=
* [https://en.wikipedia.org/wiki/Cray_T3E Cray T3E from Wikipedia]
* [https://commons.wikimedia.org/wiki/Category:Cray_T3E Category:Cray T3E - Wikimedia Commons]
* [https://en.wikipedia.org/wiki/Cray Cray (brand) from Wikipedia]
* [http://www.cray.com/ Cray, the Supercomputer Company | Cray"]
: [http://www.cray.com/company/history Company History | Cray]
* [http://www.craysupercomputers.com/crayT3E.htm Cray Super Computers - Cray T3E]
* [http://www.cray-cyber.org/systems/t3e.php Cray-Cyber - Cray T3E]
=References=
<references />
'''[[Hardware|Up one Level]]'''
[[FILE:Processor board cray-2 hg.jpg|border|right|thumb| Cray T3E processor board <ref>Processor board of a CRAY T3E-136/ac (=air-cooled) massive parallel computer (operational ca. 1997-2005). The related system had 136 processors in total. This board has four Dec-Alpha EV5 processors (300 MHz) with local memory chips and router chips onboard. [[DEC Alpha|Alpha]] processors were superscalar with two floating point operations per cycle. Authors: [https://commons.wikimedia.org/wiki/User:Hgrobe Hannes Grobe] & [http://www.awi.de/People/show?wuebber Chresten Wübber], [https://en.wikipedia.org/wiki/Alfred_Wegener_Institute_for_Polar_and_Marine_Research Alfred Wegener Institute for Polar and Marine Research], [https://en.wikipedia.org/wiki/Bremerhaven Bremerhaven], Germany, August 08 2006, [https://creativecommons.org/licenses/by-sa/2.5 CC-BY-SA-2.5], [https://en.wikipedia.org/wiki/Cray_T3E Cray T3E from Wikipedia], [https://en.wikipedia.org/wiki/Alpha_21164 Alpha 21164 from Wikipedia]</ref> ]]
'''Cray T3E''',<br/>
[https://en.wikipedia.org/wiki/Cray#Cray_Research_Inc._and_Cray_Computer_Corporation:_1972_to_1996 Cray Research's] second-generation [https://en.wikipedia.org/wiki/Massively_parallel_%28computing%29 massively parallel] [https://en.wikipedia.org/wiki/Supercomputer supercomputer] architecture, launched in 1995 as successor of the [[Cray T3D|T3D]]. The T3E is a scalable [https://en.wikipedia.org/wiki/Distributed_computing distributed] [[NUMA]] architecture containing up to 2176 processing element (PE) nodes of initially 300 MHz [[DEC Alpha|DEC Alpha 21164]] processor with 64 MiB to 2 GiB of [[Memory#RAM|DRAM]] interconnected as a [https://en.wikipedia.org/wiki/Torus_interconnect 3D torus], so that each processor can access the memory of every other processor. Later models consists of faster Alpha 21164A and 21264 processors.
=Chess Programs=
* [[Zugzwang (Program)|Zugzwang]]
=See also=
* [[Cray-1]]
* [[Cray X-MP]]
* [[Cray T3D]]
=Manuals=
* [http://www.filibeto.org/~aduritz/truetrue/supercomputing/cray/datasheets/t3e.pdf Cray T3E-1350 Datasheet] (pdf)
=Publications=
* [[Rainer Feldmann]], [[Burkhard Monien]] ('''1998'''). ''Selective Game Tree Search on a Cray T3E''. [https://pdfs.semanticscholar.org/27e6/f73eb509511c20543ddae5470259077d8dfc.pdf pdf]
* [http://dblp.uni-trier.de/pers/hd/d/Dungworth:Michael Michael Dungworth], [http://dblp.uni-trier.de/pers/hc/h/Harrell:James James Harrell], [http://dblp.uni-trier.de/pers/hc/l/Levine:Michael Michael Levine], [http://dblp.uni-trier.de/pers/hc/n/Nelson:Stephen Stephen Nelson], [http://dblp.uni-trier.de/pers/hc/o/Oberlin:Steven Steven Oberlin], [http://dblp.uni-trier.de/pers/hc/r/Reinhardt:Steven_P= Steven P. Reinhardt] ('''2011'''). ''[http://link.springer.com/referenceworkentry/10.1007%2F978-0-387-09766-4_306 CRAY T3E]''. [http://link.springer.com/book/10.1007/978-0-387-09766-4 Encyclopedia of Parallel Computing], [https://en.wikipedia.org/wiki/Springer_Science%2BBusiness_Media Springer]
=External Links=
* [https://en.wikipedia.org/wiki/Cray_T3E Cray T3E from Wikipedia]
* [https://commons.wikimedia.org/wiki/Category:Cray_T3E Category:Cray T3E - Wikimedia Commons]
* [https://en.wikipedia.org/wiki/Cray Cray (brand) from Wikipedia]
* [http://www.cray.com/ Cray, the Supercomputer Company | Cray"]
: [http://www.cray.com/company/history Company History | Cray]
* [http://www.craysupercomputers.com/crayT3E.htm Cray Super Computers - Cray T3E]
* [http://www.cray-cyber.org/systems/t3e.php Cray-Cyber - Cray T3E]
=References=
<references />
'''[[Hardware|Up one Level]]'''
