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ARM2
,Created page with "'''Home * Hardware * ARM2''' '''ARM2''', (ARM3)<br/> the Acorn RISC Machine [https://en.wikipedia.org/wiki/List_of_ARM_microarchitec..."
'''[[Main Page|Home]] * [[Hardware]] * ARM2'''
'''ARM2''', (ARM3)<br/>
the [[Acorn Computers Ltd|Acorn]] RISC Machine [https://en.wikipedia.org/wiki/List_of_ARM_microarchitectures ARMv2 architecture] is a 32-bit [https://en.wikipedia.org/wiki/CMOS CMOS] [https://en.wikipedia.org/wiki/Reduced_instruction_set_computer reduced instruction set computer], first released in 1987 <ref>[https://groups.google.com/forum/#!msg/comp.arch/hPsDLEPf2eo/nvJR_d7nnyYJ Some facts about the Acorn RISC Machine] by [https://en.wikipedia.org/wiki/Sophie_Wilson Roger Wilson], comp.arch, November 02, 1988</ref> as successor of the initial ARM (1985), designed by [https://en.wikipedia.org/wiki/Sophie_Wilson Sophie Wilson] and [https://en.wikipedia.org/wiki/Steve_Furber Steve Furber] in 1984. It features a 32-bit data bus, a [https://en.wikipedia.org/wiki/26-bit 26-bit] address space and sixteen 32-bit [https://en.wikipedia.org/wiki/Processor_register registers] (r0 - r15, including [https://en.wikipedia.org/wiki/Program_counter PC] and [https://en.wikipedia.org/wiki/Call_stack#Structure SP]) <ref>[http://www.peter-cockerell.net/aalp/html/ch-2.html ARM Assembly Language Programming - Chapter 2 - Inside the ARM]</ref>, and a 3-stage [https://en.wikipedia.org/wiki/Instruction_pipeline pipelined] (Fetch, Decode, Execute) [https://en.wikipedia.org/wiki/Von_Neumann_architecture Von Neumann architecture].
The ARM is a [[Endianness|bi endian]] machine, per default [[Little-endian|little-endian]].
<span id="Assembly"></span>
=Features=
The ARM [https://en.wikipedia.org/wiki/Instruction_set instruction set] features three operand instructions, and [https://en.wikipedia.org/wiki/ARM_architecture#Conditional_execution conditional execution] to [[Avoiding Branches|avoid conditional branches]]. Some sample ARM [[Assembly|assembly]] <ref>Samples from [https://de.wikipedia.org/wiki/ARM-Architektur#Besonderheiten_des_Befehlssatzes ARM-Architektur - Besonderheiten des Befehlssatzes | Wikipedia.de] (German)</ref> :
<pre>
CMP r0, r1 ; set flags
ADDGE r2, r2, r3 ; if (r0 >= r1) then r2 := r2 + r3;
ADDLT r2, r2, r4 ; else r2 := r2 + r4;
</pre>
A 32-bit [https://en.wikipedia.org/wiki/Barrel_shifter barrel shifter] can be used without performance penalty with most arithmetic instructions and address calculations:
<pre>
ADD r2, r3, r3, lsl #2 ; r2 := r3 + (r3 << 2)
; → r2 := r3 + r3 * 4
; → r2 := r3 * 5
</pre>
=Computer Chess=
The ARM2 processor was embedded inside the [[TASC]] [[ChessMachine]] plugged in as [https://en.wikipedia.org/wiki/ISA_bus ISA card] inside an [[IBM PC]], running [[Gideon]] and [[The King]] <ref>[https://www.schach-computer.info/wiki/index.php/TASC_ChessMachine TASC ChessMachine] from [https://www.schach-computer.info/wiki/index.php/Hauptseite_En Schachcomputer.info Wiki]</ref>, and was further used in various [[Dedicated Chess Computers|dedicated chess computers]] by [[Hegener & Glaser]] such as the [[Mephisto RISC]].
=See also=
* [[Acorn Archimedes]]
* [[ARM6]]
=Manuals=
* [http://infocenter.arm.com/help/topic/com.arm.doc.qrc0001m/QRC0001_UAL.pdf ARM® and Thumb®-2 Instruction Set Quick Reference Card] (pdf)
* [http://www.peter-cockerell.net/aalp/html/frames.html ARM Assembly Language Programming] by [http://www.peter-cockerell.net/ Pete Cockerell]
=Postings=
* [https://groups.google.com/d/msg/comp.arch/hPsDLEPf2eo/nvJR_d7nnyYJ Some facts about the Acorn RISC Machine] by [https://en.wikipedia.org/wiki/Sophie_Wilson Roger Wilson], [https://groups.google.com/forum/#!forum/comp.arch comp.arch], November 02, 1988
* [https://groups.google.com/forum/#!msg/rec.games.chess.computer/LN4AMZzpvJE/7_s4MVp7C2UJ StrongARM speed of Streater program (was Re: M-Chess Pro 6.0 program description)] by [[Stephen B. Streater]], [[Computer Chess Forums|rgcc]], October 21, 1996 » reply to [[Ed Schroder|Ed Schröder]] on [[ARM2]] vs. [[StrongARM]]
=External Links=
* [https://en.wikipedia.org/wiki/ARM_architecture#Acorn_RISC_Machine:_ARM2 Acorn RISC Machine: ARM2 from Wikipedia]
* [https://en.wikipedia.org/wiki/Amber_%28processor_core%29 Amber (processor core) from Wikipedia]
* [https://en.wikichip.org/wiki/acorn/microarchitectures/arm2 ARM2 - Microarchitectures - Acorn - WikiChip]
* [https://en.wikichip.org/wiki/acorn/microarchitectures/arm3 ARM3 - Microarchitectures - Acorn - WikiChip]
* [http://www.heyrick.co.uk/armwiki/Main_Page ARMwiki]
* [http://www.heyrick.co.uk/assembler/ ARM Assembler]
* [http://www.heyrick.co.uk/assembler/qfinder.html Instruction set quick finder]
* [https://www.schach-computer.info/wiki/index.php/ARM ARM] from [https://www.schach-computer.info/wiki/index.php/Hauptseite_En Schachcomputer.info Wiki]
* [https://en.wikipedia.org/wiki/RISC_OS RISC OS from Wikipedia]
* [https://www.riscosopen.org/wiki/documentation/show/ARM%20Hardware%20Overview ARM Hardware Overview]
* [http://infocenter.arm.com/help/index.jsp ARM Information Center]
* [https://www.realworldtech.com/arms-race/ARM’s Race to Embedded World Domination] by [https://www.realworldtech.com/author/pdemone/ Paul DeMone], [https://www.realworldtech.com/ Real World Tech], November 9, 2000
=References=
<references />
'''[[Hardware|Up one Level]]'''
'''ARM2''', (ARM3)<br/>
the [[Acorn Computers Ltd|Acorn]] RISC Machine [https://en.wikipedia.org/wiki/List_of_ARM_microarchitectures ARMv2 architecture] is a 32-bit [https://en.wikipedia.org/wiki/CMOS CMOS] [https://en.wikipedia.org/wiki/Reduced_instruction_set_computer reduced instruction set computer], first released in 1987 <ref>[https://groups.google.com/forum/#!msg/comp.arch/hPsDLEPf2eo/nvJR_d7nnyYJ Some facts about the Acorn RISC Machine] by [https://en.wikipedia.org/wiki/Sophie_Wilson Roger Wilson], comp.arch, November 02, 1988</ref> as successor of the initial ARM (1985), designed by [https://en.wikipedia.org/wiki/Sophie_Wilson Sophie Wilson] and [https://en.wikipedia.org/wiki/Steve_Furber Steve Furber] in 1984. It features a 32-bit data bus, a [https://en.wikipedia.org/wiki/26-bit 26-bit] address space and sixteen 32-bit [https://en.wikipedia.org/wiki/Processor_register registers] (r0 - r15, including [https://en.wikipedia.org/wiki/Program_counter PC] and [https://en.wikipedia.org/wiki/Call_stack#Structure SP]) <ref>[http://www.peter-cockerell.net/aalp/html/ch-2.html ARM Assembly Language Programming - Chapter 2 - Inside the ARM]</ref>, and a 3-stage [https://en.wikipedia.org/wiki/Instruction_pipeline pipelined] (Fetch, Decode, Execute) [https://en.wikipedia.org/wiki/Von_Neumann_architecture Von Neumann architecture].
The ARM is a [[Endianness|bi endian]] machine, per default [[Little-endian|little-endian]].
<span id="Assembly"></span>
=Features=
The ARM [https://en.wikipedia.org/wiki/Instruction_set instruction set] features three operand instructions, and [https://en.wikipedia.org/wiki/ARM_architecture#Conditional_execution conditional execution] to [[Avoiding Branches|avoid conditional branches]]. Some sample ARM [[Assembly|assembly]] <ref>Samples from [https://de.wikipedia.org/wiki/ARM-Architektur#Besonderheiten_des_Befehlssatzes ARM-Architektur - Besonderheiten des Befehlssatzes | Wikipedia.de] (German)</ref> :
<pre>
CMP r0, r1 ; set flags
ADDGE r2, r2, r3 ; if (r0 >= r1) then r2 := r2 + r3;
ADDLT r2, r2, r4 ; else r2 := r2 + r4;
</pre>
A 32-bit [https://en.wikipedia.org/wiki/Barrel_shifter barrel shifter] can be used without performance penalty with most arithmetic instructions and address calculations:
<pre>
ADD r2, r3, r3, lsl #2 ; r2 := r3 + (r3 << 2)
; → r2 := r3 + r3 * 4
; → r2 := r3 * 5
</pre>
=Computer Chess=
The ARM2 processor was embedded inside the [[TASC]] [[ChessMachine]] plugged in as [https://en.wikipedia.org/wiki/ISA_bus ISA card] inside an [[IBM PC]], running [[Gideon]] and [[The King]] <ref>[https://www.schach-computer.info/wiki/index.php/TASC_ChessMachine TASC ChessMachine] from [https://www.schach-computer.info/wiki/index.php/Hauptseite_En Schachcomputer.info Wiki]</ref>, and was further used in various [[Dedicated Chess Computers|dedicated chess computers]] by [[Hegener & Glaser]] such as the [[Mephisto RISC]].
=See also=
* [[Acorn Archimedes]]
* [[ARM6]]
=Manuals=
* [http://infocenter.arm.com/help/topic/com.arm.doc.qrc0001m/QRC0001_UAL.pdf ARM® and Thumb®-2 Instruction Set Quick Reference Card] (pdf)
* [http://www.peter-cockerell.net/aalp/html/frames.html ARM Assembly Language Programming] by [http://www.peter-cockerell.net/ Pete Cockerell]
=Postings=
* [https://groups.google.com/d/msg/comp.arch/hPsDLEPf2eo/nvJR_d7nnyYJ Some facts about the Acorn RISC Machine] by [https://en.wikipedia.org/wiki/Sophie_Wilson Roger Wilson], [https://groups.google.com/forum/#!forum/comp.arch comp.arch], November 02, 1988
* [https://groups.google.com/forum/#!msg/rec.games.chess.computer/LN4AMZzpvJE/7_s4MVp7C2UJ StrongARM speed of Streater program (was Re: M-Chess Pro 6.0 program description)] by [[Stephen B. Streater]], [[Computer Chess Forums|rgcc]], October 21, 1996 » reply to [[Ed Schroder|Ed Schröder]] on [[ARM2]] vs. [[StrongARM]]
=External Links=
* [https://en.wikipedia.org/wiki/ARM_architecture#Acorn_RISC_Machine:_ARM2 Acorn RISC Machine: ARM2 from Wikipedia]
* [https://en.wikipedia.org/wiki/Amber_%28processor_core%29 Amber (processor core) from Wikipedia]
* [https://en.wikichip.org/wiki/acorn/microarchitectures/arm2 ARM2 - Microarchitectures - Acorn - WikiChip]
* [https://en.wikichip.org/wiki/acorn/microarchitectures/arm3 ARM3 - Microarchitectures - Acorn - WikiChip]
* [http://www.heyrick.co.uk/armwiki/Main_Page ARMwiki]
* [http://www.heyrick.co.uk/assembler/ ARM Assembler]
* [http://www.heyrick.co.uk/assembler/qfinder.html Instruction set quick finder]
* [https://www.schach-computer.info/wiki/index.php/ARM ARM] from [https://www.schach-computer.info/wiki/index.php/Hauptseite_En Schachcomputer.info Wiki]
* [https://en.wikipedia.org/wiki/RISC_OS RISC OS from Wikipedia]
* [https://www.riscosopen.org/wiki/documentation/show/ARM%20Hardware%20Overview ARM Hardware Overview]
* [http://infocenter.arm.com/help/index.jsp ARM Information Center]
* [https://www.realworldtech.com/arms-race/ARM’s Race to Embedded World Domination] by [https://www.realworldtech.com/author/pdemone/ Paul DeMone], [https://www.realworldtech.com/ Real World Tech], November 9, 2000
=References=
<references />
'''[[Hardware|Up one Level]]'''
