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TBM
,Created page with "'''Home * Hardware * x86-64 * TBM''' '''TBM''' (Trailing Bit Manipulation Instructions),<br/> an x86-64 expansion of Bit-Twiddling#BitManipulation|bit..."
'''[[Main Page|Home]] * [[Hardware]] * [[x86-64]] * TBM'''
'''TBM''' (Trailing Bit Manipulation Instructions),<br/>
an x86-64 expansion of [[Bit-Twiddling#BitManipulation|bit-manipulation]] instructions, introduced by [[AMD]] with the [https://en.wikipedia.org/wiki/Bulldozer_%28microarchitecture%29 Bulldozer microarchitecture], which also comprises the [[AVX]], [[BMI1]] and [[XOP]] instruction sets. TBM requires bit 21 set in ECX of CPUID EAX=80000001H <ref>[http://support.amd.com/us/Embedded_TechDocs/25481.pdf AMD CPUID Specification] (pdf)</ref>.
More recent [https://en.wikipedia.org/wiki/Jaguar_(microarchitecture) AMD Jaguar] and [https://en.wikipedia.org/wiki/Zen_(microarchitecture) Zen] based processors do not support TBM <ref>[https://www.amd.com/system/files/TechDocs/52169_KB_A_Series_Mobile.pdf Family 16h Models 00h-0Fh AMD A-Series Mobile Accelerated Processor Product Data Sheet] (pdf)</ref>.
=Instructions=
TBM offers various bit-manipulations based on the [[General Setwise Operations#TheLeastSignificantOneBitLS1B|least significant one]] or [[General Setwise Operations#TheLeastSignificantZeroBitLS0B|zero bit]]. In general they combine two or three [[General Setwise Operations|operations]] on 32- or 64-bit general purpose registers, expanding the [[BMI1|BMI]] type of operations of [[BMI1#BLSI|BLSI]], [[BMI1#BLSMSK|BLSMSK]], [[BMI1#BLSR|BLSR]]. In [[C]] and [[Cpp|C++]], these instructions should be emitted by an optimizing compiler for this target platform, rather than using intrinsics. Instructions are given with [https://en.wikipedia.org/wiki/Assembly_language#Opcode_mnemonics_and_extended_mnemonics mnemonics] with 64-bit destination and source register according to [[Assembly#x86Syntax|Intel Syntax]], [[C]] like definition, and some arbitrary [[Bitboards|bitboard]] diagrams with [[Square Mapping Considerations#LittleEndianRankFileMapping|little-endian rank-file mapping]] (least significant bit 0 as square a1 bottom-left) to illustrate the operations.
{{MappingHint}}
<span id="BLSFILL"></span>
==Least Significant One Bit==
===BLSFILL===
Fill From Lowest Set Bit. [[General Setwise Operations#Union|Union]] with the decrement.
<pre>
BLSFILL reg64, reg/mem64
dest ::= src | (src - 1);
src | (src - 1) = dest
0x0040201008040200 0x00402010080401FF 0x00402010080403FF
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 1 . . . . . . . 1 . . . . . . . 1 .
. . . . . 1 . . . . . . . 1 . . . . . . . 1 . .
. . . . 1 . . . . . . . 1 . . . . . . . 1 . . .
. . . 1 . . . . | . . . 1 . . . . = . . . 1 . . . .
. . 1 . . . . . . . 1 . . . . . . . 1 . . . . .
. 1 . . . . . . 1 . . . . . . . 1 1 . . . . . .
. . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
</pre>
<span id="BLSIC"></span>
===BLSIC===
Isolate Lowest Set Bit and Complement. [[General Setwise Operations#Union|Union]] of [[General Setwise Operations#ComplementSet|complement]] and decrement.
<pre>
BLSIC reg64, reg/mem64
dest ::= ~src | (src - 1);
src -> ~src | (src - 1) = dest
0x0040201008040200 0x00402010080401FF 0x00402010080403FF 0xFFFFFFFFFFFFFDFF
. . . . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1
. . . . . . 1 . 1 1 1 1 1 1 . 1 . . . . . . 1 . 1 1 1 1 1 1 1 1
. . . . . 1 . . 1 1 1 1 1 . 1 1 . . . . . 1 . . 1 1 1 1 1 1 1 1
. . . . 1 . . . 1 1 1 1 . 1 1 1 . . . . 1 . . . 1 1 1 1 1 1 1 1
. . . 1 . . . . -> 1 1 1 . 1 1 1 1 | . . . 1 . . . . = 1 1 1 1 1 1 1 1
. . 1 . . . . . 1 1 . 1 1 1 1 1 . . 1 . . . . . 1 1 1 1 1 1 1 1
. 1 . . . . . . 1 . 1 1 1 1 1 1 1 . . . . . . . 1 . 1 1 1 1 1 1
. . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
</pre>
<span id="TZMSK"></span>
===TZMSK===
Mask From Trailing Zeros. [[General Setwise Operations#Intersection|Intersection]] of [[General Setwise Operations#ComplementSet|complement]] and decrement [[General Setwise Operations#LS1BSeparation|sets all bits below]] the [[General Setwise Operations#TheLeastSignificantOneBitLS1B|least significant one bit]], and clears all other bits, including the LS1B itself.
<pre>
dest ::= ~src & (src - 1);
src -> ~src & (src - 1) = dest
0x0040201008040200 0x00402010080401FF 0x00402010080403FF 0x00000000000001FF
. . . . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . . .
. . . . . . 1 . 1 1 1 1 1 1 . 1 . . . . . . 1 . . . . . . . . .
. . . . . 1 . . 1 1 1 1 1 . 1 1 . . . . . 1 . . . . . . . . . .
. . . . 1 . . . 1 1 1 1 . 1 1 1 . . . . 1 . . . . . . . . . . .
. . . 1 . . . . -> 1 1 1 . 1 1 1 1 & . . . 1 . . . . = . . . . . . . .
. . 1 . . . . . 1 1 . 1 1 1 1 1 . . 1 . . . . . . . . . . . . .
. 1 . . . . . . 1 . 1 1 1 1 1 1 1 . . . . . . . 1 . . . . . . .
. . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
</pre>
<span id="BLCFILL"></span>
==Least Significant Zero Bit==
===BLCFILL===
Fill From Lowest Clear Bit. [[General Setwise Operations#Intersection|Intersection]] with the increment.
<pre>
BLCFILL reg64, reg/mem64
dest ::= src & (src + 1);
src & (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x80C0E0F0F8FCFF00 0x80C0E0F0F8FCFE00
. . . . . . . 1 . . . . . . . 1 . . . . . . . 1
. . . . . . 1 1 . . . . . . 1 1 . . . . . . 1 1
. . . . . 1 1 1 . . . . . 1 1 1 . . . . . 1 1 1
. . . . 1 1 1 1 . . . . 1 1 1 1 . . . . 1 1 1 1
. . . 1 1 1 1 1 & . . . 1 1 1 1 1 = . . . 1 1 1 1 1
. . 1 1 1 1 1 1 . . 1 1 1 1 1 1 . . 1 1 1 1 1 1
. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . . .
</pre>
<span id="BLCI"></span>
===BLCI===
Isolate Lowest Clear Bit. [[General Setwise Operations#Union|Union]] with the [[General Setwise Operations#ComplementSet|complement]] of the increment.
<pre>
BLCI reg64, reg/mem64
dest ::= src | ~(src + 1);
src | ~(src + 1) = dest
0x80C0E0F0F8FCFEFF 0x7F3F1F0F070300FF 0xFFFFFFFFFFFFFEFF
. . . . . . . 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
. . . . . . 1 1 1 1 1 1 1 1 . . 1 1 1 1 1 1 1 1
. . . . . 1 1 1 1 1 1 1 1 . . . 1 1 1 1 1 1 1 1
. . . . 1 1 1 1 1 1 1 1 . . . . 1 1 1 1 1 1 1 1
. . . 1 1 1 1 1 | 1 1 1 . . . . . = 1 1 1 1 1 1 1 1
. . 1 1 1 1 1 1 1 1 . . . . . . 1 1 1 1 1 1 1 1
. 1 1 1 1 1 1 1 . . . . . . . . . 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
</pre>
<span id="BLCIC"></span>
===BLCIC===
Isolate Lowest Clear Bit and Complement. [[General Setwise Operations#Intersection|Intersection]] of the [[General Setwise Operations#ComplementSet|complement]] with the increment.
<pre>
BLCIC reg64, reg/mem64
dest ::= ~src & (src + 1);
src -> ~src & (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x7F3F1F0F07030100 0x80C0E0F0F8FCFF00 0x0000000000000100
. . . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 . . . . . . . .
. . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 . . . . . . . .
. . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 . . . . . . . .
. . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 . . . . . . . .
. . . 1 1 1 1 1 -> 1 1 1 . . . . . & . . . 1 1 1 1 1 = . . . . . . . .
. . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 . . . . . . . .
. 1 1 1 1 1 1 1 1 . . . . . . . 1 1 1 1 1 1 1 1 1 . . . . . . .
1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . . . . . . . . . . .
</pre>
<span id="BLCMSK"></span>
===BLCMSK===
Mask From Lowest Clear Bit. [[General Setwise Operations#ExclusiveOr|Exclusive or]] with the increment.
<pre>
BLCMSK reg64, reg/mem64
dest ::= src ^ (src + 1);
src ^ (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x80C0E0F0F8FCFF00 0x00000000000001FF
. . . . . . . 1 . . . . . . . 1 . . . . . . . .
. . . . . . 1 1 . . . . . . 1 1 . . . . . . . .
. . . . . 1 1 1 . . . . . 1 1 1 . . . . . . . .
. . . . 1 1 1 1 . . . . 1 1 1 1 . . . . . . . .
. . . 1 1 1 1 1 ^ . . . 1 1 1 1 1 = . . . . . . . .
. . 1 1 1 1 1 1 . . 1 1 1 1 1 1 . . . . . . . .
. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 . . . . . . .
1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1
</pre>
<span id="BLCS"></span>
===BLCS===
Set Lowest Clear Bit. [[General Setwise Operations#Union|Union]] with the increment.
<pre>
BLCS reg64, reg/mem64
dest ::= src | (src + 1);
src | (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x80C0E0F0F8FCFF00 0x80C0E0F0F8FCFFFF
. . . . . . . 1 . . . . . . . 1 . . . . . . . 1
. . . . . . 1 1 . . . . . . 1 1 . . . . . . 1 1
. . . . . 1 1 1 . . . . . 1 1 1 . . . . . 1 1 1
. . . . 1 1 1 1 . . . . 1 1 1 1 . . . . 1 1 1 1
. . . 1 1 1 1 1 | . . . 1 1 1 1 1 = . . . 1 1 1 1 1
. . 1 1 1 1 1 1 . . 1 1 1 1 1 1 . . 1 1 1 1 1 1
. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1
</pre>
<span id="T1MSKC"></span>
===T1MSKC===
Inverse Mask From Trailing Ones. [[General Setwise Operations#Union|Union]] of [[General Setwise Operations#ComplementSet|complement]] and increment.
<pre>
T1MSKC reg64, reg/mem64
dest ::= ~src | (src + 1);
src -> ~src | (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x7F3F1F0F07030100 0x80C0E0F0F8FCFF00 0xFFFFFFFFFFFFFF00
. . . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1
. . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1 1
. . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1 1 1
. . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1
. . . 1 1 1 1 1 -> 1 1 1 . . . . . | . . . 1 1 1 1 1 = 1 1 1 1 1 1 1 1
. . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1
. 1 1 1 1 1 1 1 1 . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . . . . . . . . . . .
</pre>
<span id="BEXTR"></span>
==Misc==
===BEXTR===
An immediate form of the variable [[BMI1#BEXTR|BMI1 Bit Field Extract]].
<pre>
BEXTR reg32, reg/mem32, imm32
BEXTR reg64, reg/mem64, imm32
</pre>
=See also=
* [[SSE4#ABM|ABM]]
* [[Bit-Twiddling]]
* [[BMI1]]
* [[BMI2]]
* [[General Setwise Operations]]
: [[General Setwise Operations#TheLeastSignificantOneBitLS1B|Obtaining and Clearing the Least Significant Bit (LS1B)]]
=Manuals=
* [https://www.amd.com/system/files/TechDocs/24594.pdf AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions] (pdf) <ref>Moved BMI and TBM instructions from Volume 4 to Volume 3 in September 2011</ref>
* [https://www.amd.com/system/files/TechDocs/47414_15h_sw_opt_guide.pdf Software Optimization Guide for AMD Family 15h Processors] (pdf) 9.8 Optimizing with BMI and TBM Instructions, pp. 163
=External Links=
* [https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation) TBM from Wikipedia]
=References=
<references />
'''[[x86-64|Up one Level]]'''
'''TBM''' (Trailing Bit Manipulation Instructions),<br/>
an x86-64 expansion of [[Bit-Twiddling#BitManipulation|bit-manipulation]] instructions, introduced by [[AMD]] with the [https://en.wikipedia.org/wiki/Bulldozer_%28microarchitecture%29 Bulldozer microarchitecture], which also comprises the [[AVX]], [[BMI1]] and [[XOP]] instruction sets. TBM requires bit 21 set in ECX of CPUID EAX=80000001H <ref>[http://support.amd.com/us/Embedded_TechDocs/25481.pdf AMD CPUID Specification] (pdf)</ref>.
More recent [https://en.wikipedia.org/wiki/Jaguar_(microarchitecture) AMD Jaguar] and [https://en.wikipedia.org/wiki/Zen_(microarchitecture) Zen] based processors do not support TBM <ref>[https://www.amd.com/system/files/TechDocs/52169_KB_A_Series_Mobile.pdf Family 16h Models 00h-0Fh AMD A-Series Mobile Accelerated Processor Product Data Sheet] (pdf)</ref>.
=Instructions=
TBM offers various bit-manipulations based on the [[General Setwise Operations#TheLeastSignificantOneBitLS1B|least significant one]] or [[General Setwise Operations#TheLeastSignificantZeroBitLS0B|zero bit]]. In general they combine two or three [[General Setwise Operations|operations]] on 32- or 64-bit general purpose registers, expanding the [[BMI1|BMI]] type of operations of [[BMI1#BLSI|BLSI]], [[BMI1#BLSMSK|BLSMSK]], [[BMI1#BLSR|BLSR]]. In [[C]] and [[Cpp|C++]], these instructions should be emitted by an optimizing compiler for this target platform, rather than using intrinsics. Instructions are given with [https://en.wikipedia.org/wiki/Assembly_language#Opcode_mnemonics_and_extended_mnemonics mnemonics] with 64-bit destination and source register according to [[Assembly#x86Syntax|Intel Syntax]], [[C]] like definition, and some arbitrary [[Bitboards|bitboard]] diagrams with [[Square Mapping Considerations#LittleEndianRankFileMapping|little-endian rank-file mapping]] (least significant bit 0 as square a1 bottom-left) to illustrate the operations.
{{MappingHint}}
<span id="BLSFILL"></span>
==Least Significant One Bit==
===BLSFILL===
Fill From Lowest Set Bit. [[General Setwise Operations#Union|Union]] with the decrement.
<pre>
BLSFILL reg64, reg/mem64
dest ::= src | (src - 1);
src | (src - 1) = dest
0x0040201008040200 0x00402010080401FF 0x00402010080403FF
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 1 . . . . . . . 1 . . . . . . . 1 .
. . . . . 1 . . . . . . . 1 . . . . . . . 1 . .
. . . . 1 . . . . . . . 1 . . . . . . . 1 . . .
. . . 1 . . . . | . . . 1 . . . . = . . . 1 . . . .
. . 1 . . . . . . . 1 . . . . . . . 1 . . . . .
. 1 . . . . . . 1 . . . . . . . 1 1 . . . . . .
. . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
</pre>
<span id="BLSIC"></span>
===BLSIC===
Isolate Lowest Set Bit and Complement. [[General Setwise Operations#Union|Union]] of [[General Setwise Operations#ComplementSet|complement]] and decrement.
<pre>
BLSIC reg64, reg/mem64
dest ::= ~src | (src - 1);
src -> ~src | (src - 1) = dest
0x0040201008040200 0x00402010080401FF 0x00402010080403FF 0xFFFFFFFFFFFFFDFF
. . . . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1
. . . . . . 1 . 1 1 1 1 1 1 . 1 . . . . . . 1 . 1 1 1 1 1 1 1 1
. . . . . 1 . . 1 1 1 1 1 . 1 1 . . . . . 1 . . 1 1 1 1 1 1 1 1
. . . . 1 . . . 1 1 1 1 . 1 1 1 . . . . 1 . . . 1 1 1 1 1 1 1 1
. . . 1 . . . . -> 1 1 1 . 1 1 1 1 | . . . 1 . . . . = 1 1 1 1 1 1 1 1
. . 1 . . . . . 1 1 . 1 1 1 1 1 . . 1 . . . . . 1 1 1 1 1 1 1 1
. 1 . . . . . . 1 . 1 1 1 1 1 1 1 . . . . . . . 1 . 1 1 1 1 1 1
. . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
</pre>
<span id="TZMSK"></span>
===TZMSK===
Mask From Trailing Zeros. [[General Setwise Operations#Intersection|Intersection]] of [[General Setwise Operations#ComplementSet|complement]] and decrement [[General Setwise Operations#LS1BSeparation|sets all bits below]] the [[General Setwise Operations#TheLeastSignificantOneBitLS1B|least significant one bit]], and clears all other bits, including the LS1B itself.
<pre>
dest ::= ~src & (src - 1);
src -> ~src & (src - 1) = dest
0x0040201008040200 0x00402010080401FF 0x00402010080403FF 0x00000000000001FF
. . . . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . . .
. . . . . . 1 . 1 1 1 1 1 1 . 1 . . . . . . 1 . . . . . . . . .
. . . . . 1 . . 1 1 1 1 1 . 1 1 . . . . . 1 . . . . . . . . . .
. . . . 1 . . . 1 1 1 1 . 1 1 1 . . . . 1 . . . . . . . . . . .
. . . 1 . . . . -> 1 1 1 . 1 1 1 1 & . . . 1 . . . . = . . . . . . . .
. . 1 . . . . . 1 1 . 1 1 1 1 1 . . 1 . . . . . . . . . . . . .
. 1 . . . . . . 1 . 1 1 1 1 1 1 1 . . . . . . . 1 . . . . . . .
. . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
</pre>
<span id="BLCFILL"></span>
==Least Significant Zero Bit==
===BLCFILL===
Fill From Lowest Clear Bit. [[General Setwise Operations#Intersection|Intersection]] with the increment.
<pre>
BLCFILL reg64, reg/mem64
dest ::= src & (src + 1);
src & (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x80C0E0F0F8FCFF00 0x80C0E0F0F8FCFE00
. . . . . . . 1 . . . . . . . 1 . . . . . . . 1
. . . . . . 1 1 . . . . . . 1 1 . . . . . . 1 1
. . . . . 1 1 1 . . . . . 1 1 1 . . . . . 1 1 1
. . . . 1 1 1 1 . . . . 1 1 1 1 . . . . 1 1 1 1
. . . 1 1 1 1 1 & . . . 1 1 1 1 1 = . . . 1 1 1 1 1
. . 1 1 1 1 1 1 . . 1 1 1 1 1 1 . . 1 1 1 1 1 1
. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . . .
</pre>
<span id="BLCI"></span>
===BLCI===
Isolate Lowest Clear Bit. [[General Setwise Operations#Union|Union]] with the [[General Setwise Operations#ComplementSet|complement]] of the increment.
<pre>
BLCI reg64, reg/mem64
dest ::= src | ~(src + 1);
src | ~(src + 1) = dest
0x80C0E0F0F8FCFEFF 0x7F3F1F0F070300FF 0xFFFFFFFFFFFFFEFF
. . . . . . . 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
. . . . . . 1 1 1 1 1 1 1 1 . . 1 1 1 1 1 1 1 1
. . . . . 1 1 1 1 1 1 1 1 . . . 1 1 1 1 1 1 1 1
. . . . 1 1 1 1 1 1 1 1 . . . . 1 1 1 1 1 1 1 1
. . . 1 1 1 1 1 | 1 1 1 . . . . . = 1 1 1 1 1 1 1 1
. . 1 1 1 1 1 1 1 1 . . . . . . 1 1 1 1 1 1 1 1
. 1 1 1 1 1 1 1 . . . . . . . . . 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
</pre>
<span id="BLCIC"></span>
===BLCIC===
Isolate Lowest Clear Bit and Complement. [[General Setwise Operations#Intersection|Intersection]] of the [[General Setwise Operations#ComplementSet|complement]] with the increment.
<pre>
BLCIC reg64, reg/mem64
dest ::= ~src & (src + 1);
src -> ~src & (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x7F3F1F0F07030100 0x80C0E0F0F8FCFF00 0x0000000000000100
. . . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 . . . . . . . .
. . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 . . . . . . . .
. . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 . . . . . . . .
. . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 . . . . . . . .
. . . 1 1 1 1 1 -> 1 1 1 . . . . . & . . . 1 1 1 1 1 = . . . . . . . .
. . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 . . . . . . . .
. 1 1 1 1 1 1 1 1 . . . . . . . 1 1 1 1 1 1 1 1 1 . . . . . . .
1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . . . . . . . . . . .
</pre>
<span id="BLCMSK"></span>
===BLCMSK===
Mask From Lowest Clear Bit. [[General Setwise Operations#ExclusiveOr|Exclusive or]] with the increment.
<pre>
BLCMSK reg64, reg/mem64
dest ::= src ^ (src + 1);
src ^ (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x80C0E0F0F8FCFF00 0x00000000000001FF
. . . . . . . 1 . . . . . . . 1 . . . . . . . .
. . . . . . 1 1 . . . . . . 1 1 . . . . . . . .
. . . . . 1 1 1 . . . . . 1 1 1 . . . . . . . .
. . . . 1 1 1 1 . . . . 1 1 1 1 . . . . . . . .
. . . 1 1 1 1 1 ^ . . . 1 1 1 1 1 = . . . . . . . .
. . 1 1 1 1 1 1 . . 1 1 1 1 1 1 . . . . . . . .
. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 . . . . . . .
1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1
</pre>
<span id="BLCS"></span>
===BLCS===
Set Lowest Clear Bit. [[General Setwise Operations#Union|Union]] with the increment.
<pre>
BLCS reg64, reg/mem64
dest ::= src | (src + 1);
src | (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x80C0E0F0F8FCFF00 0x80C0E0F0F8FCFFFF
. . . . . . . 1 . . . . . . . 1 . . . . . . . 1
. . . . . . 1 1 . . . . . . 1 1 . . . . . . 1 1
. . . . . 1 1 1 . . . . . 1 1 1 . . . . . 1 1 1
. . . . 1 1 1 1 . . . . 1 1 1 1 . . . . 1 1 1 1
. . . 1 1 1 1 1 | . . . 1 1 1 1 1 = . . . 1 1 1 1 1
. . 1 1 1 1 1 1 . . 1 1 1 1 1 1 . . 1 1 1 1 1 1
. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1
</pre>
<span id="T1MSKC"></span>
===T1MSKC===
Inverse Mask From Trailing Ones. [[General Setwise Operations#Union|Union]] of [[General Setwise Operations#ComplementSet|complement]] and increment.
<pre>
T1MSKC reg64, reg/mem64
dest ::= ~src | (src + 1);
src -> ~src | (src + 1) = dest
0x80C0E0F0F8FCFEFF 0x7F3F1F0F07030100 0x80C0E0F0F8FCFF00 0xFFFFFFFFFFFFFF00
. . . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1
. . . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1 1
. . . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1 1 1
. . . . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1
. . . 1 1 1 1 1 -> 1 1 1 . . . . . | . . . 1 1 1 1 1 = 1 1 1 1 1 1 1 1
. . 1 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1
. 1 1 1 1 1 1 1 1 . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 . . . . . . . . . . . . . . . . . . . . . . . .
</pre>
<span id="BEXTR"></span>
==Misc==
===BEXTR===
An immediate form of the variable [[BMI1#BEXTR|BMI1 Bit Field Extract]].
<pre>
BEXTR reg32, reg/mem32, imm32
BEXTR reg64, reg/mem64, imm32
</pre>
=See also=
* [[SSE4#ABM|ABM]]
* [[Bit-Twiddling]]
* [[BMI1]]
* [[BMI2]]
* [[General Setwise Operations]]
: [[General Setwise Operations#TheLeastSignificantOneBitLS1B|Obtaining and Clearing the Least Significant Bit (LS1B)]]
=Manuals=
* [https://www.amd.com/system/files/TechDocs/24594.pdf AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions] (pdf) <ref>Moved BMI and TBM instructions from Volume 4 to Volume 3 in September 2011</ref>
* [https://www.amd.com/system/files/TechDocs/47414_15h_sw_opt_guide.pdf Software Optimization Guide for AMD Family 15h Processors] (pdf) 9.8 Optimizing with BMI and TBM Instructions, pp. 163
=External Links=
* [https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation) TBM from Wikipedia]
=References=
<references />
'''[[x86-64|Up one Level]]'''
