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I860
,Created page with "'''Home * Hardware * i860''' [[FILE:Intel 80860XR die2.JPG|border|right|thumb| [https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 Die] shot of i860..."
'''[[Main Page|Home]] * [[Hardware]] * i860'''
[[FILE:Intel 80860XR die2.JPG|border|right|thumb| [https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 Die] shot of i860 XR <ref>[https://commons.wikimedia.org/wiki/File:Intel_80860XR_die2.JPG Die shot of Intel 80860XR] microprocessor (A80860XR-40, SX438) by [https://commons.wikimedia.org/wiki/User:Birdman86 Pauli Rautakorpi], April 25, 2014, [https://creativecommons.org/licenses/by/3.0/deed.en CC BY 3.0], [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons], [https://de.wikipedia.org/wiki/Intel_i860 Intel i860 from Wikipedia.de] (German)</ref> ]]
'''i860''', (80860)<br/>
was a 32/64-bit [https://en.wikipedia.org/wiki/Reduced_instruction_set_computing RISC] [https://en.wikipedia.org/wiki/Microprocessor microprocessor] introduced in 1989 by [[Intel]]. The first '''i860 XR''' ran at 25, 33, or 40 MHz. The second generation '''i860 XP''' added larger on-chip first level [[Memory#Cache|caches]], second level cache support, and hardware support for [https://en.wikipedia.org/wiki/Bus_sniffing bus snooping] for [https://en.wikipedia.org/wiki/Cache_coherence cache consistency] in [https://en.wikipedia.org/wiki/Multiprocessing multiprocessor] systems <ref>[https://en.wikipedia.org/wiki/Intel_i860 Intel i860 from Wikipeida]</ref>. Due to several [https://en.wikipedia.org/wiki/Intel_i860#Performance_.28problems.29 performance problems], the i860 never achieved commercial success and the project was abandoned in the mid-1990s.
=Architecture=
The processor had a [https://en.wikipedia.org/wiki/Very_long_instruction_word VLIW] [https://en.wikipedia.org/wiki/Microarchitecture architecture] with two [https://en.wikipedia.org/wiki/Classic_RISC_pipeline pipelines] <ref>[http://blog.garritys.org/2010/04/intel-i860.html From Here to There - Intel i860] by [http://blog.garritys.org/author/mike Mike Garrity], April 06, 2010</ref>, a 32-bit integer [[Combinatorial Logic#ALU|ALU]] "core", and a three part 64-bit [https://en.wikipedia.org/wiki/Floating-point_unit FPU] or [[SIMD and SWAR Techniques|SIMD]] unit consisting of an adder, multiplier, and a 3D-graphics unit. Core integer execution was applied using 32 32-bit registers r0 through r31, also used for address computation. [https://en.wikipedia.org/wiki/IEEE_754-1985 IEEE 754] [[Float|floats]] or vectors of [[Byte|bytes]] and [[Word|words]] are kept in 32 32-bit registers f0 through f31, which can also be configured as 16 x 64 (i.e. for IEEE 754 [[Double|double]]) or 8 x 128-bit vector registers. When accessing 128-bit values, a aligned set of four registers was used, addressed by f0, f4, ..., f28. The i860 FP and SIMD design influenced the later [[MMX]] extension of [[x86]] processors, the [https://en.wikipedia.org/wiki/P5_%28microarchitecture%29 Pentium MMX] in 1998.
=Paragon=
The [[Paragon]] was a series of [https://en.wikipedia.org/wiki/Massively_parallel_%28computing%29 massively parallel] [https://en.wikipedia.org/wiki/Supercomputer supercomputers] by [[Intel]] based on the i860. Up to 2048 (later, up to 4000) i860s were connected in a 2D grid.
=Chess Programs=
* [[Petunia]]
* [[Star Socrates|*Socrates]] ([[Paragon]])
=Manuals=
* [http://bitsavers.trailing-edge.com/pdf/intel/i860/240875-001_i860_64-Bit_Microprocessor_Programmers_Reference_May91.pdf Intel® i860™ Microprocessor Family Programmer's Reference Manual 1991] (pdf from [http://www.mirrorservice.org/sites/www.bitsavers.org/ bitsavers.org])
* [http://allthingsd.com/20131023/dadi-perlmutter-to-leave-intel-early-next-year/ David Perlmutter], [http://www.opentechisrael.org/#!untitled/c1ah7 Michael Kagan] ('''1991'''). ''The i860™ XP Second Generation of the i860™ Supercomputing Microprocessor Family''. [http://www.hotchips.org/wp-content/uploads/hc_archives/hc03/2_Mon/HC3.S3/HC3.3.2.pdf pdf]
=External Links=
* [https://en.wikipedia.org/wiki/Intel_i860 Intel i860 from Wikipeida]
* [http://smithsonianchips.si.edu/intel/i860.htm The Chip Collection - i860 Microprocessor], [https://en.wikipedia.org/wiki/Smithsonian_Institution Smithsonian Institution]
* [http://www.cpu-world.com/CPUs/80860/ Intel 80860 (i860) CPU family]
* [http://blog.garritys.org/2010/04/intel-i860.html From Here to There - Intel i860] by [http://blog.garritys.org/author/mike Mike Garrity], April 06, 2010
* [https://en.wikipedia.org/wiki/Intel_Paragon Intel Paragon from Wikipedia]
=References=
<references />
'''[[Hardware|Up one Level]]'''
[[Category:Die]]
[[FILE:Intel 80860XR die2.JPG|border|right|thumb| [https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29 Die] shot of i860 XR <ref>[https://commons.wikimedia.org/wiki/File:Intel_80860XR_die2.JPG Die shot of Intel 80860XR] microprocessor (A80860XR-40, SX438) by [https://commons.wikimedia.org/wiki/User:Birdman86 Pauli Rautakorpi], April 25, 2014, [https://creativecommons.org/licenses/by/3.0/deed.en CC BY 3.0], [https://en.wikipedia.org/wiki/Wikimedia_Commons Wikimedia Commons], [https://de.wikipedia.org/wiki/Intel_i860 Intel i860 from Wikipedia.de] (German)</ref> ]]
'''i860''', (80860)<br/>
was a 32/64-bit [https://en.wikipedia.org/wiki/Reduced_instruction_set_computing RISC] [https://en.wikipedia.org/wiki/Microprocessor microprocessor] introduced in 1989 by [[Intel]]. The first '''i860 XR''' ran at 25, 33, or 40 MHz. The second generation '''i860 XP''' added larger on-chip first level [[Memory#Cache|caches]], second level cache support, and hardware support for [https://en.wikipedia.org/wiki/Bus_sniffing bus snooping] for [https://en.wikipedia.org/wiki/Cache_coherence cache consistency] in [https://en.wikipedia.org/wiki/Multiprocessing multiprocessor] systems <ref>[https://en.wikipedia.org/wiki/Intel_i860 Intel i860 from Wikipeida]</ref>. Due to several [https://en.wikipedia.org/wiki/Intel_i860#Performance_.28problems.29 performance problems], the i860 never achieved commercial success and the project was abandoned in the mid-1990s.
=Architecture=
The processor had a [https://en.wikipedia.org/wiki/Very_long_instruction_word VLIW] [https://en.wikipedia.org/wiki/Microarchitecture architecture] with two [https://en.wikipedia.org/wiki/Classic_RISC_pipeline pipelines] <ref>[http://blog.garritys.org/2010/04/intel-i860.html From Here to There - Intel i860] by [http://blog.garritys.org/author/mike Mike Garrity], April 06, 2010</ref>, a 32-bit integer [[Combinatorial Logic#ALU|ALU]] "core", and a three part 64-bit [https://en.wikipedia.org/wiki/Floating-point_unit FPU] or [[SIMD and SWAR Techniques|SIMD]] unit consisting of an adder, multiplier, and a 3D-graphics unit. Core integer execution was applied using 32 32-bit registers r0 through r31, also used for address computation. [https://en.wikipedia.org/wiki/IEEE_754-1985 IEEE 754] [[Float|floats]] or vectors of [[Byte|bytes]] and [[Word|words]] are kept in 32 32-bit registers f0 through f31, which can also be configured as 16 x 64 (i.e. for IEEE 754 [[Double|double]]) or 8 x 128-bit vector registers. When accessing 128-bit values, a aligned set of four registers was used, addressed by f0, f4, ..., f28. The i860 FP and SIMD design influenced the later [[MMX]] extension of [[x86]] processors, the [https://en.wikipedia.org/wiki/P5_%28microarchitecture%29 Pentium MMX] in 1998.
=Paragon=
The [[Paragon]] was a series of [https://en.wikipedia.org/wiki/Massively_parallel_%28computing%29 massively parallel] [https://en.wikipedia.org/wiki/Supercomputer supercomputers] by [[Intel]] based on the i860. Up to 2048 (later, up to 4000) i860s were connected in a 2D grid.
=Chess Programs=
* [[Petunia]]
* [[Star Socrates|*Socrates]] ([[Paragon]])
=Manuals=
* [http://bitsavers.trailing-edge.com/pdf/intel/i860/240875-001_i860_64-Bit_Microprocessor_Programmers_Reference_May91.pdf Intel® i860™ Microprocessor Family Programmer's Reference Manual 1991] (pdf from [http://www.mirrorservice.org/sites/www.bitsavers.org/ bitsavers.org])
* [http://allthingsd.com/20131023/dadi-perlmutter-to-leave-intel-early-next-year/ David Perlmutter], [http://www.opentechisrael.org/#!untitled/c1ah7 Michael Kagan] ('''1991'''). ''The i860™ XP Second Generation of the i860™ Supercomputing Microprocessor Family''. [http://www.hotchips.org/wp-content/uploads/hc_archives/hc03/2_Mon/HC3.S3/HC3.3.2.pdf pdf]
=External Links=
* [https://en.wikipedia.org/wiki/Intel_i860 Intel i860 from Wikipeida]
* [http://smithsonianchips.si.edu/intel/i860.htm The Chip Collection - i860 Microprocessor], [https://en.wikipedia.org/wiki/Smithsonian_Institution Smithsonian Institution]
* [http://www.cpu-world.com/CPUs/80860/ Intel 80860 (i860) CPU family]
* [http://blog.garritys.org/2010/04/intel-i860.html From Here to There - Intel i860] by [http://blog.garritys.org/author/mike Mike Garrity], April 06, 2010
* [https://en.wikipedia.org/wiki/Intel_Paragon Intel Paragon from Wikipedia]
=References=
<references />
'''[[Hardware|Up one Level]]'''
[[Category:Die]]
