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'''[[Main Page|Home]] * [[Hardware]] * Fairchild F8'''
'''Fairchild F8''',<br/>
an [https://en.wikipedia.org/wiki/8-bit 8-bit] multi-chip [https://en.wikipedia.org/wiki/Microcontroller microcontroller] by [https://en.wikipedia.org/wiki/Fairchild_Semiconductor Fairchild Semiconductor] introduced and launched in 1975. The F8 consists of the '''3850''' [https://en.wikipedia.org/wiki/Central_processing_unit CPU] with 8-bit [[Combinatorial Logic#ALU|ALU]], 64-bytes [[Memory#Latches|scratchpad RAM]] and two 8-bit [https://en.wikipedia.org/wiki/Input/output I/O] ports, the '''3851''' program storage unit (PSU) with 2 KiB [[Memory#ROM|ROM]], the '''3852''' [[Memory#DynamicRAM|dynamic memory]] interface (MI), and '''3853''' [[Memory#StaticRAM|static memory]] (or ROM) interface (SMI) chip, the optional '''3854''' [https://en.wikipedia.org/wiki/Channel_I/O DMA controller], and the '''3861'''/'''3871''' [https://en.wikipedia.org/wiki/Parallel_I/O parallel I/O] (PIO) chips. A minimal system could be build from a 3850 with either a 3851 or a 3853 with external ROM. The [https://en.wikipedia.org/wiki/Mostek#Microprocessor_second_sourcing_deals Mostek 3870] was a 3850/3851 single-chip implementation with some extra 64 bytes RAM, launched in 1977 <ref>[http://www.cpu-world.com/CPUs/3870/index.html Mostek 3870 (MK3870) microcontroller family from CPU world]</ref> .
=Details=
==Circuit Diagram==
[[FILE:F8.JPG|none|border|text-bottom|link=https://usermanual.wiki/Document/FairchildF8Kit1schematicrevC1975.1174772138/html]]
F8 Kit [https://en.wikipedia.org/wiki/Circuit_diagram circuit diagram] <ref>[https://usermanual.wiki/Document/FairchildF8Kit1schematicrevC1975.1174772138/html Fairchild F8 Kit 1 Schematic, Revision C, 25 Sep 1975], [https://usermanual.wiki/ User Manual Wiki]</ref>
==Registers==
The 3850 CPU has an 8-bit [https://en.wikipedia.org/wiki/Accumulator_%28computing%29 accumulator] as input and output of the ALU, as well a 5-bit [https://en.wikipedia.org/wiki/Status_register status register] to indicate the flags [https://en.wikipedia.org/wiki/Negative_flag sign], [https://en.wikipedia.org/wiki/Carry_flag carry], [https://en.wikipedia.org/wiki/Zero_flag zero] and [https://en.wikipedia.org/wiki/Overflow_flag overflow] after arithmetical and logical operations, as well as an [https://en.wikipedia.org/wiki/Programmable_Interrupt_Controller interrupt control] bit to enable or disable [https://en.wikipedia.org/wiki/Interrupt interrupts]. The 64 byte scratchpad memory allow [https://en.wikipedia.org/wiki/Addressing_mode#Register_indirect_2 indirect addressing] mode via the ISAR (indirect scratchpad register), which could be used as a kind of [[Stack|stack]] pointer to a stack frame of 8 bytes.
16-bit [https://en.wikipedia.org/wiki/Program_counter progam counter], stack register, data counter (DC to indirectly address up 64 KiB of memory), and address incrementer/adder were not part of the CPU, but in each PSU and/or MI. There is no [https://en.wikipedia.org/wiki/Address_bus address bus] from the CPU, but a set of control signals, and transfer of addresses, i.e. branch targets, via the [https://en.wikipedia.org/wiki/Data_bus data bus]. The stack register is directly linked to the program counter and simplifies the creation of a [https://en.wikipedia.org/wiki/Call_stack call stack].
==Instructions==
Arithmetical and logical [https://en.wikipedia.org/wiki/Instruction_set instructions] work on the accumulator. Source operands are either implicit, content of scratchpad register, indirect addressed via [https://en.wikipedia.org/wiki/Increment_and_decrement_operators post-incremented] data counter (DC) register, or immediate <ref>[http://bitsavers.informatik.uni-stuttgart.de/pdf/fairchild/f8/F8_prelimUM_Jan75.pdf F8 Prelimanary Microprocessor User's Manual] (pdf) Circuit Organization, Machine Instructions, F8 Cross Assembler, F8 Cross Simulator, from [http://bitsavers.informatik.uni-stuttgart.de/ bitsavers.org]</ref> :
{| class="wikitable"
|-
! Mnemonic
! Description
! Operation
! Bytes
! Cycles
|-
| NI ii
| And with immediate
| ACC &= ii
| style="text-align:center;" | 2
| style="text-align:center;" | 2.5
|-
| NS rn
| And with scratchpad r0..63
| ACC &= rn
| style="text-align:center;" | 1
| style="text-align:center;" | 1
|-
| NM
| And via post-incremented DC
| ACC &= *DC++
| style="text-align:center;" | 1
| style="text-align:center;" | 2.5
|}
==Endianess==
F8 is a [[Big-endian|big-endian]] machine concerning the [[Byte|byte]]-order of 16-bit [[Word|words]] in (scratchpad) memory. For instance, LR PO,Q, restore Q register contents to the program counter, has the upper byte in scratchpad register r14, and the lower byte in r15.
==Sample Assembly==
A answer back program in F8 [[Assembly]] as given by David Edwards, [https://en.wikipedia.org/wiki/Electronics_Australia Electronics Australia] <ref>David Edwards ('''1976'''). ''The Mostek F8''. [https://en.wikipedia.org/wiki/Electronics_Australia Electronics Australia], December, 1976, [http://messui.the-chronicles.org/comp/fairchild.pdf pdf]</ref> :
<pre>
ANSWER-BACK PROGRAM FOR MOSTEK F8 EVALUATION KIT
D. EDWARDS, ELECTRONICS AUSTRALIA 19/10/76
0400 20 FF INIT,LI FF /LOAD AC WITH FF
0402 OB LR IS,A /INITIALIZE ISAR TO 3F
0403 54 LR 4,A /COPY AC INTO REG 4
0404 34 DS 4 /DECREMENT REG 4 TO FE
0405 56 LR 6,A /COPY AC INTO REG 6
0406 71 LIS H'1' /LOAD AC WITH 01
0407 B6 OUTS 6 /TRANSFER AC TO TIMER PORT TO ENABLE EXT INT
0408 1B EI /ENABLE I/O ROUTINES
0409 20 03 F3 START,PI 03F3 /CALL TTYIN SUBROUTINE
040C 4C LR AS /COPY CHAR INTO AC FROM RS
040D 25 OD CI 'OD' /COMPARE WITH CR
040F 84 06 BZ MESSAGE /JUMP TO MESSAGE IF CR
0411 28 03 5D PI 035D /SEND CHAR TO TTYOUT SUBROUTINE
0414 90 F4 BR START /LOOP BACK TO START
0416 2A 04 23 MESSAGE,DCI 0423 /LOAD DC WITH MESSAGE ADDRESS
0419 70 ANSWER,CLR /CLEAR AC
041A 88 AM /ADD CHAR TO AC AND INC DC
041B 84 ED BZ START /LOOP BACK TO START
041D 5C LR S,A /COPY CHAR INTO RS
041E 28 03 5D PI 035D /SEND CHAR TO TTYOUT SUBROUTINE
0421 90 F7 BR ANSWER /LOOP BACK TO ANSWER
0423 OD 47 4F /START OF ANSWER BUFFER
0426 20 41 57
0429 41 59 2C
042C 20 49 27
043F 4D 20 42
0432 55 53 59
0435 21 OD 00 /ANSWER MUST END WITH A ZERO BYTE
</pre>
=F8 Chess Computers=
The original [[CompuChess]] <ref>[http://www.schach-computer.info/wiki/index.php/CompuChess CompuChess] from [http://www.schach-computer.info/wiki/index.php/Hauptseite_En Schachcomputer.info - Wiki] by [[Mike Watters]]</ref> and its [[Clones|clone]], the [[Novag]] [[Chess Champion MK I]] had the '''3850''' CPU and the '''3853''' SMI, addressing a 2 KiB 2316 compatible ROM, and 2 x 2111 <ref>[http://pdf1.alldatasheet.com/datasheet-pdf/view/125751/NSC/MM2111.html MM2111 pdf, MM2111 description, MM2111 datasheets, MM2111 view]</ref> 256x4 each, in total 256 byte SRAM <ref>[http://www.schach-computer.info/wiki/index.php/Novag_Chess_Champion_MK_I Novag Chess Champion MK I] from [http://www.schach-computer.info/wiki/index.php/Hauptseite_En Schachcomputer.info - Wiki] (German)</ref> . [[Boris]] also used the 3850/3853 approach with 2 x 2112 for 256 byte SRAM, and 2 x 2 KiB ROM <ref>[http://alain.zanchetta.free.fr/docs/AppliedConcepts/BorisKitAssemblyManualUS.pdf Boris assembly manual] (pdf) hosted by [[Alain Zanchetta]]</ref> . [[David Kittinger]] had to solve the 128 byte challenge (including scratchpad) for the [[Novag Micro Chess]] with [https://en.wikipedia.org/wiki/Mostek#Microprocessor_second_sourcing_deals Mostek 3870].
* [[Boris]]
* [[Chess Champion MK I]]
* [[Chess Champion Pocket Chess]]
* [[Chess Partner 2000]]
* [[CompuChess]]
* [[Novag Micro Chess]]
* [[SABA Videoplay 20]]
=External Links=
* [https://en.wikipedia.org/wiki/Fairchild_F8 Fairchild F8 from Wikipedia]
* [http://www.borischesscomputer.com/fairchildprocessor.htm Fairchild processor - BORIS IS KING]
* [http://www.cpu-world.com/CPUs/3850/index.html Fairchild F8 (3850) microcontroller family from CPU world]
* [http://www.cpushack.com/2013/06/08/cpu-of-the-day-fairchild-f8-microprocessor/ CPU of the Day: Fairchild F8 Microprocessor | The CPU Shack Museum], June 8, 2013
* [http://www.cpu-world.com/CPUs/3870/index.html Mostek 3870 (MK3870) microcontroller family from CPU world]
* [http://www.google.com/patents/US4086626 Patent US4086626 - Microprocessor system - Google Patents]
* [http://seanriddle.com/f8info.html F8 info] by [[Sean Riddle]]
* [https://en.wikipedia.org/wiki/Fairchild_Channel_F Fairchild Channel F from Wikipedia]
* [http://dasm-dillon.sourceforge.net/ the dasm macro assembler]
* [http://xi6.com/projects/asmx/ asmx multi-CPU assembler]
=References=
<references />
'''[[Hardware|Up one Level]]'''
'''Fairchild F8''',<br/>
an [https://en.wikipedia.org/wiki/8-bit 8-bit] multi-chip [https://en.wikipedia.org/wiki/Microcontroller microcontroller] by [https://en.wikipedia.org/wiki/Fairchild_Semiconductor Fairchild Semiconductor] introduced and launched in 1975. The F8 consists of the '''3850''' [https://en.wikipedia.org/wiki/Central_processing_unit CPU] with 8-bit [[Combinatorial Logic#ALU|ALU]], 64-bytes [[Memory#Latches|scratchpad RAM]] and two 8-bit [https://en.wikipedia.org/wiki/Input/output I/O] ports, the '''3851''' program storage unit (PSU) with 2 KiB [[Memory#ROM|ROM]], the '''3852''' [[Memory#DynamicRAM|dynamic memory]] interface (MI), and '''3853''' [[Memory#StaticRAM|static memory]] (or ROM) interface (SMI) chip, the optional '''3854''' [https://en.wikipedia.org/wiki/Channel_I/O DMA controller], and the '''3861'''/'''3871''' [https://en.wikipedia.org/wiki/Parallel_I/O parallel I/O] (PIO) chips. A minimal system could be build from a 3850 with either a 3851 or a 3853 with external ROM. The [https://en.wikipedia.org/wiki/Mostek#Microprocessor_second_sourcing_deals Mostek 3870] was a 3850/3851 single-chip implementation with some extra 64 bytes RAM, launched in 1977 <ref>[http://www.cpu-world.com/CPUs/3870/index.html Mostek 3870 (MK3870) microcontroller family from CPU world]</ref> .
=Details=
==Circuit Diagram==
[[FILE:F8.JPG|none|border|text-bottom|link=https://usermanual.wiki/Document/FairchildF8Kit1schematicrevC1975.1174772138/html]]
F8 Kit [https://en.wikipedia.org/wiki/Circuit_diagram circuit diagram] <ref>[https://usermanual.wiki/Document/FairchildF8Kit1schematicrevC1975.1174772138/html Fairchild F8 Kit 1 Schematic, Revision C, 25 Sep 1975], [https://usermanual.wiki/ User Manual Wiki]</ref>
==Registers==
The 3850 CPU has an 8-bit [https://en.wikipedia.org/wiki/Accumulator_%28computing%29 accumulator] as input and output of the ALU, as well a 5-bit [https://en.wikipedia.org/wiki/Status_register status register] to indicate the flags [https://en.wikipedia.org/wiki/Negative_flag sign], [https://en.wikipedia.org/wiki/Carry_flag carry], [https://en.wikipedia.org/wiki/Zero_flag zero] and [https://en.wikipedia.org/wiki/Overflow_flag overflow] after arithmetical and logical operations, as well as an [https://en.wikipedia.org/wiki/Programmable_Interrupt_Controller interrupt control] bit to enable or disable [https://en.wikipedia.org/wiki/Interrupt interrupts]. The 64 byte scratchpad memory allow [https://en.wikipedia.org/wiki/Addressing_mode#Register_indirect_2 indirect addressing] mode via the ISAR (indirect scratchpad register), which could be used as a kind of [[Stack|stack]] pointer to a stack frame of 8 bytes.
16-bit [https://en.wikipedia.org/wiki/Program_counter progam counter], stack register, data counter (DC to indirectly address up 64 KiB of memory), and address incrementer/adder were not part of the CPU, but in each PSU and/or MI. There is no [https://en.wikipedia.org/wiki/Address_bus address bus] from the CPU, but a set of control signals, and transfer of addresses, i.e. branch targets, via the [https://en.wikipedia.org/wiki/Data_bus data bus]. The stack register is directly linked to the program counter and simplifies the creation of a [https://en.wikipedia.org/wiki/Call_stack call stack].
==Instructions==
Arithmetical and logical [https://en.wikipedia.org/wiki/Instruction_set instructions] work on the accumulator. Source operands are either implicit, content of scratchpad register, indirect addressed via [https://en.wikipedia.org/wiki/Increment_and_decrement_operators post-incremented] data counter (DC) register, or immediate <ref>[http://bitsavers.informatik.uni-stuttgart.de/pdf/fairchild/f8/F8_prelimUM_Jan75.pdf F8 Prelimanary Microprocessor User's Manual] (pdf) Circuit Organization, Machine Instructions, F8 Cross Assembler, F8 Cross Simulator, from [http://bitsavers.informatik.uni-stuttgart.de/ bitsavers.org]</ref> :
{| class="wikitable"
|-
! Mnemonic
! Description
! Operation
! Bytes
! Cycles
|-
| NI ii
| And with immediate
| ACC &= ii
| style="text-align:center;" | 2
| style="text-align:center;" | 2.5
|-
| NS rn
| And with scratchpad r0..63
| ACC &= rn
| style="text-align:center;" | 1
| style="text-align:center;" | 1
|-
| NM
| And via post-incremented DC
| ACC &= *DC++
| style="text-align:center;" | 1
| style="text-align:center;" | 2.5
|}
==Endianess==
F8 is a [[Big-endian|big-endian]] machine concerning the [[Byte|byte]]-order of 16-bit [[Word|words]] in (scratchpad) memory. For instance, LR PO,Q, restore Q register contents to the program counter, has the upper byte in scratchpad register r14, and the lower byte in r15.
==Sample Assembly==
A answer back program in F8 [[Assembly]] as given by David Edwards, [https://en.wikipedia.org/wiki/Electronics_Australia Electronics Australia] <ref>David Edwards ('''1976'''). ''The Mostek F8''. [https://en.wikipedia.org/wiki/Electronics_Australia Electronics Australia], December, 1976, [http://messui.the-chronicles.org/comp/fairchild.pdf pdf]</ref> :
<pre>
ANSWER-BACK PROGRAM FOR MOSTEK F8 EVALUATION KIT
D. EDWARDS, ELECTRONICS AUSTRALIA 19/10/76
0400 20 FF INIT,LI FF /LOAD AC WITH FF
0402 OB LR IS,A /INITIALIZE ISAR TO 3F
0403 54 LR 4,A /COPY AC INTO REG 4
0404 34 DS 4 /DECREMENT REG 4 TO FE
0405 56 LR 6,A /COPY AC INTO REG 6
0406 71 LIS H'1' /LOAD AC WITH 01
0407 B6 OUTS 6 /TRANSFER AC TO TIMER PORT TO ENABLE EXT INT
0408 1B EI /ENABLE I/O ROUTINES
0409 20 03 F3 START,PI 03F3 /CALL TTYIN SUBROUTINE
040C 4C LR AS /COPY CHAR INTO AC FROM RS
040D 25 OD CI 'OD' /COMPARE WITH CR
040F 84 06 BZ MESSAGE /JUMP TO MESSAGE IF CR
0411 28 03 5D PI 035D /SEND CHAR TO TTYOUT SUBROUTINE
0414 90 F4 BR START /LOOP BACK TO START
0416 2A 04 23 MESSAGE,DCI 0423 /LOAD DC WITH MESSAGE ADDRESS
0419 70 ANSWER,CLR /CLEAR AC
041A 88 AM /ADD CHAR TO AC AND INC DC
041B 84 ED BZ START /LOOP BACK TO START
041D 5C LR S,A /COPY CHAR INTO RS
041E 28 03 5D PI 035D /SEND CHAR TO TTYOUT SUBROUTINE
0421 90 F7 BR ANSWER /LOOP BACK TO ANSWER
0423 OD 47 4F /START OF ANSWER BUFFER
0426 20 41 57
0429 41 59 2C
042C 20 49 27
043F 4D 20 42
0432 55 53 59
0435 21 OD 00 /ANSWER MUST END WITH A ZERO BYTE
</pre>
=F8 Chess Computers=
The original [[CompuChess]] <ref>[http://www.schach-computer.info/wiki/index.php/CompuChess CompuChess] from [http://www.schach-computer.info/wiki/index.php/Hauptseite_En Schachcomputer.info - Wiki] by [[Mike Watters]]</ref> and its [[Clones|clone]], the [[Novag]] [[Chess Champion MK I]] had the '''3850''' CPU and the '''3853''' SMI, addressing a 2 KiB 2316 compatible ROM, and 2 x 2111 <ref>[http://pdf1.alldatasheet.com/datasheet-pdf/view/125751/NSC/MM2111.html MM2111 pdf, MM2111 description, MM2111 datasheets, MM2111 view]</ref> 256x4 each, in total 256 byte SRAM <ref>[http://www.schach-computer.info/wiki/index.php/Novag_Chess_Champion_MK_I Novag Chess Champion MK I] from [http://www.schach-computer.info/wiki/index.php/Hauptseite_En Schachcomputer.info - Wiki] (German)</ref> . [[Boris]] also used the 3850/3853 approach with 2 x 2112 for 256 byte SRAM, and 2 x 2 KiB ROM <ref>[http://alain.zanchetta.free.fr/docs/AppliedConcepts/BorisKitAssemblyManualUS.pdf Boris assembly manual] (pdf) hosted by [[Alain Zanchetta]]</ref> . [[David Kittinger]] had to solve the 128 byte challenge (including scratchpad) for the [[Novag Micro Chess]] with [https://en.wikipedia.org/wiki/Mostek#Microprocessor_second_sourcing_deals Mostek 3870].
* [[Boris]]
* [[Chess Champion MK I]]
* [[Chess Champion Pocket Chess]]
* [[Chess Partner 2000]]
* [[CompuChess]]
* [[Novag Micro Chess]]
* [[SABA Videoplay 20]]
=External Links=
* [https://en.wikipedia.org/wiki/Fairchild_F8 Fairchild F8 from Wikipedia]
* [http://www.borischesscomputer.com/fairchildprocessor.htm Fairchild processor - BORIS IS KING]
* [http://www.cpu-world.com/CPUs/3850/index.html Fairchild F8 (3850) microcontroller family from CPU world]
* [http://www.cpushack.com/2013/06/08/cpu-of-the-day-fairchild-f8-microprocessor/ CPU of the Day: Fairchild F8 Microprocessor | The CPU Shack Museum], June 8, 2013
* [http://www.cpu-world.com/CPUs/3870/index.html Mostek 3870 (MK3870) microcontroller family from CPU world]
* [http://www.google.com/patents/US4086626 Patent US4086626 - Microprocessor system - Google Patents]
* [http://seanriddle.com/f8info.html F8 info] by [[Sean Riddle]]
* [https://en.wikipedia.org/wiki/Fairchild_Channel_F Fairchild Channel F from Wikipedia]
* [http://dasm-dillon.sourceforge.net/ the dasm macro assembler]
* [http://xi6.com/projects/asmx/ asmx multi-CPU assembler]
=References=
<references />
'''[[Hardware|Up one Level]]'''
