422
edits
Changes
m
→SIMD Instruction Sets: added VMX RISC-V + cleanup
* [[SSE2]], [[SSE3]], [[SSSE3]] and [[SSE4]] on [[x86]] and [[x86-64]]
* [[SSE5]] by [[AMD]] (proposed but not implemented, replaced by [[XOP]] <ref>[https://en.wikipedia.org/wiki/SSE5 SSE5 from Wikipedia]</ref>)
* [[AltiVec]] on [[PowerPC#G4|PowerPC G4]], [[PowerPC#G5|PowerPC G5]] resp. VMX since [[POWER | POWER6]]* [[VMX]https://en.wikipedia.org/wiki/AltiVec#VSX_(Vector_Scalar_Extension) VSX] since [[POWER | POWER6POWER7]]* [[Helium]] by [[ARM Helium]]* [[NEON]] by [[ARM NEON]]* [[ARM SVE]] <ref>[https://en.wikipedia.org/wiki/AArch64#Scalable_Vector_Extension_(SVE) SVE from Wikipedia]</ref>, and [[ARM SVE2]] <ref>[https://en.wikipedia.org/wiki/AArch64#ARMv8.5-A_and_ARMv9.0-A[24] SVE2 from Wikipedia]</ref>by [[ARM]]
* [[AVX]] by [[Intel]]
* [[AVX2]] by [[Intel]]
* [[AVX-512]] by [[Intel]]
* [[XOP]] by [[AMD]]
* [[VIS]] <ref>[https://en.wikipedia.org/wiki/Visual_Instruction_Set VIS from Wikipedia]</ref> since [[SPARC VIS (]] v9)* [[RISC-V]] vector-set extension <ref>[https://en.wikipedia.org/wiki/RISC-V#Vector_set RISC-V vector-set from Wikipedia]</ref>
<span id="SWAR"></span>
