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AVX-512

10 bytes added, 19:25, 30 May 2021
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Reg:Bit <ref>[https://www.heise.de/ct/zcontent/17/16-hocmsmeta/1501873687265857/ct.1617.016-017.qxp_table_29578.html AVX512 table] from [https://en.wikipedia.org/wiki/Heinz_Heise Heise]</ref>
|-
| AVX-512F 512 F
| Foundation
| rowspan="4" | [https://en.wikipedia.org/wiki/Xeon_Phi#Knights_Landing Knights Landing]
| EBX:16
|-
| AVX-512CD 512 CD
| Conflict Detection Instructions
| EBX:28
|-
| AVX-512ER 512 ER
| Exponential and Reciprocal Instructions
| EBX:27
|-
| AVX-512PF 512 PF
| Prefetch Instructions
| EBX:26
|-
| AVX-512BW 512 BW
| [[Byte]] and [[Word]] Instructions
| rowspan="3" | [https://en.wikipedia.org/wiki/Skylake_(microarchitecture) Skylake X]
| EBX:30
|-
| AVX-512DQ 512 DQ
| [[Double Word|Doubleword]] and [[Quad Word|Quadword]] Instructions
| EBX:17
|-
| AVX-512VL 512 VL
| Vector Length Extensions
| EBX:31
|-
| AVX-512IFMA 512 IFMA
| Integer Fused Multiply Add
| rowspan="2" | [https://en.wikipedia.org/wiki/Cannonlake Cannonlake]
| EBX:21
|-
| AVX-512VBMI 512 VBMI
| Vector Byte Manipulation Instructions
| ECX:01
|-
| AVX-512VPOPCNTDQ 512 VPOPCNTDQ
| Vector [[Population Count]]
| rowspan="3" | [https://en.wikipedia.org/wiki/Xeon_Phi#Knights_Mill Knights Mill]
| EDX:03
|-
| AVX-512-VNNI
| Vector Neural Network Instructions <br/>Vector Instructions for [[Deep Learning]]
| rowspan="4" | [https://en.wikipedia.org/wiki/Ice_Lake_(microprocessor) Ice Lake]
| ECX:11
|-
| AVX-512-VBMI2
| Vector Byte Manipulation Instructions 2<br/>[[Byte]]/[[Word]] Load, Store and Concatenation with Shift
|
|-
| AVX-512-BITALG
| Bit Algorithms<br/>Byte/Word Bit Manipulation Instructions expanding VPOPCNTDQn
|
|-
| AVX-512-GFNI
| Galois field New Instructions<br/>Vector Instructions for calculating [https://en.wikipedia.org/wiki/Finite_field Galois Field] GF(2^8)
|

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