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Created page with "'''Home * People * Zvonko Vranesic''' FILE:vranesic-zvonko.jpg|border|right|thumb|200px|link=http://www.croatia.org/crown/articles/10863/1/Zvonko-Vranesic..."
'''[[Main Page|Home]] * [[People]] * Zvonko Vranesic'''
[[FILE:vranesic-zvonko.jpg|border|right|thumb|200px|link=http://www.croatia.org/crown/articles/10863/1/Zvonko-Vranesic-Croatian-Canadian-International-Chess-Master-and-Professor-at-the-University-of-Toronto.html| Zvonko Vranesic <ref>[http://www.croatia.org/crown/articles/10863/1/Zvonko-Vranesic-Croatian-Canadian-International-Chess-Master-and-Professor-at-the-University-of-Toronto.html Zvonko Vranesic Croatian-Canadian International Chess Master and Professor at the University of Toronto]</ref> ]]
'''Zvonko George Vranesic''',<br/>
a [https://en.wikipedia.org/wiki/Croatian_Canadians Croatian Canadian] chess and [https://en.wikipedia.org/wiki/Correspondence_Chess correspondence chess] [https://en.wikipedia.org/wiki/FIDE_titles#International_Master_.28IM.29 international master] <ref>[http://www.eecg.toronto.edu/%7Ezvonko/bio.html Biography - Z.G. Vranesic]</ref> , [https://en.wikipedia.org/wiki/Electrical_engineer electrical engineer], and [https://en.wikipedia.org/wiki/Professor_Emeritus professor emeritus] at Depature of Electrical and Computer Engineering, Computer Engineering Research Group, [[University of Toronto]]. His research interests covers [https://en.wikipedia.org/wiki/Multi-valued_logic Multiple-Valued Logic Systems], [https://en.wikipedia.org/wiki/Parallel_computing parallel computing] along with [[NUMA]], and [[FPGA]], beside other books on that topics, along with Stephen Brown <ref>[http://www.eecg.toronto.edu/%7Ebrown/ Professor Stephen Brown - University of Toronto]</ref>, he co-authored ''Fundamentals of Digital Logic'' with [https://en.wikipedia.org/wiki/VHDL VHDL] (2000) and [https://en.wikipedia.org/wiki/Verilog Verilog] Design.
=Chute=
In the 70s, along with his student [[Michael Valenti]], Zvonko Vranesic was co-author of [[Chute]] (CHess, University of Toronto, Engineering). He supervised Valenti's 1974 Masters Thesis <ref>[[Michael Valenti]] ('''1974'''). ''CHUTE I, An Easily Modifiable Chess Playing Program''. M.A.Sc. thesis, Depature of Electrical Engineering, [[University of Toronto]]</ref> , and co-authored ''Experiences with Chute'' after the [[WCCC 1977]] in the Proceedings of the 1977 annual [[ACM]] conference <ref>[[Michael Valenti]], [[Zvonko Vranesic]] ('''1977'''). ''[http://portal.acm.org/citation.cfm?id=810241 Experiences with CHUTE]''. Proceedings of the [[ACM]] conference</ref> .
=Chess Player=
Zvonko Vranesic represented Canada at five [https://en.wikipedia.org/wiki/Chess_Olympiad Chess Olympiads] <ref>[https://en.wikipedia.org/wiki/Zvonko_Vranesic#Olympiads Zvonko Vranesic - Olympiads]</ref> , he scored a [https://en.wikipedia.org/wiki/Grandmaster_%28chess%29 Grandmaster] norm at the [https://en.wikipedia.org/wiki/19th_Chess_Olympiad 19th Chess Olympiad] in [https://en.wikipedia.org/wiki/Siegen Siegen] <ref>[https://en.wikipedia.org/wiki/Zvonko_Vranesic Zvonko Vranesic from Wikipedia]</ref>. Notable are his wins against [https://en.wikipedia.org/wiki/Leonid_Stein Leonid Stein] at the [https://en.wikipedia.org/wiki/16th_Chess_Olympiad 16th Olympiad] in [https://en.wikipedia.org/wiki/Tel_Aviv Tel Aviv] 1964 <ref>[http://www.chessgames.com/perl/chessgame?gid=1132287, Dr. Zvonko Vranesic vs Leonid Stein] from [http://www.chessgames.com/index.html chessgames.com]
</ref>, and versus [[David Levy]] in [https://en.wikipedia.org/wiki/Lone_Pine,_California Lone Pine] 1975 <ref>[http://www.chessgames.com/perl/chessgame?gid=1434722, David Neil Lawrence Levy vs Dr. Zvonko Vranesic] from [http://www.chessgames.com/index.html chessgames.com]</ref> .
=Selected Games=
==Leonid Stein==
<pre>
[Event "Olympiad"]
[Site "Tel Aviv (Israel)"]
[Date "1964.??.??"]
[Round "?"]
[Result "1-0"]
[White "Dr. Zvonko Vranesic"]
[Black "Leonid Stein"]
1.d4 Nf6 2.c4 c5 3.d5 d6 4.Nc3 g6 5.e4 Bg7 6.Nf3 O-O 7.Be2 e6 8.O-O exd5 9.cxd5 Re8
10.Nd2 Na6 11.Re1 Nc7 12.Qc2 Rb8 13.a4 Na6 14.Bxa6 bxa6 15.Nc4 Rb4 16.Na2 Nxd5 17.Bd2 Rxc4
18.Qxc4 Nb6 19.Qc2 Qh4 20.Bc3 Bh6 21.Rad1 Nc4 22.Qe2 Be6 23.Nc1 Bf8 24.Nd3 Nb6 25.Qc2 Bd7
26.g3 Qg4 27.Nf4 Nxa4 28.Nd5 Re6 29.f3 Qg5 30.f4 Qd8 31.f5 gxf5 32.exf5 Rh6 33.Bd2 Rh5
34.Rf1 Bg7 35.Be3 Bc6 36.Qe4 Kh8 37.Qg4 Rh6 38.f6 Rxf6 39.Nxf6 Bxf6 40.Rxf6 Qxf6 41.Qc8+ Kg7
1-0
</pre>
==David Levy==
<pre>
[Event "Lone Pine"]
[Site "Lone Pine"]
[Date "1975.??.??"]
[Round "08"]
[Result "0-1"]
[White "David Neil Lawrence Levy"]
[Black "Dr. Zvonko Vranesic"]
1.e4 c5 2.Nf3 e6 3.d4 cxd4 4.Nxd4 Nc6 5.Nc3 d6 6.Bc4 Nf6 7.Be3 Be7 8.Qe2 a6 9.Bb3 O-O
10.O-O-O Qc7 11.Kb1 Nxd4 12.Bxd4 b5 13.e5 dxe5 14.Bxe5 Qc6 15.f3 Bb7 16.Rd4 Rfd8
17.Rhd1 Rxd4 18.Rxd4 Rd8 19.Rxd8+ Bxd8 20.Qd3 Be7 21.Qd4 Qc5 22.Ne2 Qxd4 23.Bxd4 Bd6
24.h3 e5 25.Be3 e4 26.f4 Nd5 27.Bxd5 Bxd5 28.b3 f5 29.Kb2 Kf7 30.Kc3 g6 31.Kd4 Ke6
32.Kc3 Bb7 33.Nd4+ Kd5 34.b4 Bc8 35.h4 Be7 36.g3 Bf6 37.a3 Be6 38.Bg1 h6 39.Be3 Bf7
40.Bg1 g5 41.hxg5 hxg5 42.fxg5 Be5 43.Bf2 Bg6 44.Be3 Bxg3 45.Ne2 Be5+ 46.Kb3 Bh5
0-1
</pre>
=Selected Publications=
<ref>[https://dblp.uni-trier.de/pers/hd/v/Vranesic:Zvonko_G= dblp: Zvonko G. Vranesic]</ref>
==1970 ...==
* [[Zvonko Vranesic]], [https://www.ece.utoronto.ca/news/e-s-lee-tribute/ E. Stewart Lee], [https://en.wikipedia.org/wiki/Kenneth_C._Smith Kenneth C. Smith] ('''1970'''). ''A Many-Valued Algebra for Switching Systems''. [[IEEE#TOC|IEEE Transactions on Computers]], Vol. 19, No. 10
* [[Zvonko Vranesic]], [https://en.wikipedia.org/wiki/Kenneth_C._Smith Kenneth C. Smith] ('''1974'''). ''Engineering aspects of multi-valued logic systems''. [[IEEE#TOC|IEEE Transactions on Computers]], Vol. 7, No. 9
* [[Michael Valenti]], [[Zvonko Vranesic]] ('''1977'''). ''[http://portal.acm.org/citation.cfm?id=810241 Experiences with CHUTE]''. [[ACM]] conference
* [[Zvonko Vranesic]] ('''1977'''). ''Multiple-Valued Logic: An Introduction and Overview''. [[IEEE#TOC|IEEE Transactions on Computers]], Vol. 26, No. 12
==1980 ...==
* [https://en.wikipedia.org/wiki/Hussein_T._Mouftah Hussein T. Mouftah], [https://en.wikipedia.org/wiki/Kenneth_C._Smith Kenneth C. Smith], [[Zvonko Vranesic]] ('''1980'''). ''Ternary Rate-Multipliers''. [[IEEE#TOC|IEEE Transactions on Computers]], Vol. 29, No. 10
* [https://dblp.uni-trier.de/pers/hd/r/Rose:Jonathan Jonathan Rose], [https://dblp.uni-trier.de/pers/hd/l/Loucks:Wayne_M= Wayne M. Loucks], [[Zvonko Vranesic]] ('''1985'''). ''[https://ieeexplore.ieee.org/document/4089459/ FERMTOR: A Tunable Multiprocessor Architecture]''. [[IEEE#Micro|IEEE Micro]], Vol. 5, No. 4
* [https://dblp.uni-trier.de/pers/hd/r/Rose:Jonathan Jonathan Rose], [https://dblp.uni-trier.de/pers/hd/s/Snelgrove:W=_Martin W. Martin Snelgrove], [[Zvonko Vranesic]] ('''1988'''). ''[https://ieeexplore.ieee.org/document/3172/ Parallel standard cell placement algorithms with quality equivalent to simulated annealing]''. [[IEEE#TCICS|IEEE Transactions on CAD of Integrated Circuits and Systems]], Vol. 7, No. 3
==1990 ...==
* [[Zeljko Zilic]], [[Zvonko Vranesic]] ('''1993'''). ''[https://ieeexplore.ieee.org/document/289552/ Current-Mode CMOS Galois Field Circuits]''. [https://dblp.uni-trier.de/db/conf/ismvl/ismvl1993.html ISMVL 1993]
* [[Zeljko Zilic]], [[Zvonko Vranesic]] ('''1995'''). ''[https://ieeexplore.ieee.org/document/403717/ A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions]''. [[IEEE#TOC|IEEE Transactions on Computers]], Vol. 44, No. 8 <ref>[https://en.wikipedia.org/wiki/Reed%E2%80%93Muller_code Reed–Muller code from Wikipedia]</ref>
* [[Zeljko Zilic]], [[Zvonko Vranesic]] ('''1996'''). ''[https://www.computer.org/csdl/proceedings/fpga/1996/2576/00/25760024-abs.html Using BDDs to Design ULMs for FPGAs]''. [https://dblp.uni-trier.de/db/conf/fpga/fpga96.html FPGA 1996]
* [[Zvonko Vranesic]] ('''1998'''). ''[https://ieeexplore.ieee.org/document/679318/ The FPGA Challenge]''. [https://dblp.uni-trier.de/db/conf/ismvl/ismvl1998.html ISMVL 1998]
* [https://www.linkedin.com/in/ante-grbi%C4%87-0657665b/ Ante Grbić], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [https://dblp.uni-trier.de/pers/hd/c/Caranci:S= Steve Caranci], [https://www.linkedin.com/in/robin-grindley-47550/ Robin Grindley], [https://dblp.uni-trier.de/pers/hd/g/Gusat:Mitchell Mitchell Gusat], [http://www.ece.ubc.ca/~lemieux/ Guy Lemieux], [https://dblp.uni-trier.de/pers/hd/l/Loveless:K= K. Loveless], [https://dblp.uni-trier.de/pers/hd/m/Manjikian:Naraig Naraig Manjikian], [https://www.linkedin.com/in/sinisasrbljic/ Sinisa Srbljic], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=67137 Michael Stumm], [[Zvonko Vranesic]], [[Zeljko Zilic]] ('''1998'''). ''[https://ieeexplore.ieee.org/document/724441/ Design and Implementation of the NUMAchine Multiprocessor]''. [https://dblp.uni-trier.de/db/conf/dac/dac98.html DAC 1998], [http://www.eecg.toronto.edu/parallel/parallel/docs/dac98.pdf pdf] <ref>[http://www.eecg.toronto.edu/parallel/parallel/numadocs.html Documentation on the NUMAchine Multiprocessor]</ref>
* [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''1999'''). ''[http://www.mhhe.com/engcs/electrical/brownvranesic/ Fundamentals of Digital Logic with VHDL Design]''. [http://catalogs.mhhe.com/mhhe/home.do McGraw-Hill]
==2000 ...==
* [https://www.linkedin.com/in/robin-grindley-47550/ Robin Grindley], [http://www.eecg.toronto.edu/~tsa/ Tarek Abdelrahman], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [https://dblp.uni-trier.de/pers/hd/c/Caranci:S= Steve Caranci], [https://dblp.uni-trier.de/pers/hd/d/DeVries:D= D. DeVries], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=67177 Benjamin Gamsa], [https://www.linkedin.com/in/ante-grbi%C4%87-0657665b/ Ante Grbić], [https://dblp.uni-trier.de/pers/hd/g/Gusat:Mitchell Mitchell Gusat], [https://dblp.uni-trier.de/pers/hd/h/Ho:R= R. Ho], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=99397 Orran Krieger], [http://www.ece.ubc.ca/~lemieux/ Guy Lemieux], [https://dblp.uni-trier.de/pers/hd/l/Loveless:K= K. Loveless], [https://dblp.uni-trier.de/pers/hd/m/Manjikian:Naraig Naraig Manjikian], [https://dblp.uni-trier.de/pers/hd/m/McHardy:P= P. McHardy], [https://www.linkedin.com/in/sinisasrbljic/ Sinisa Srbljic], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=67137 Michael Stumm], [[Zvonko Vranesic]], [[Zeljko Zilic]] ('''2000'''). ''The NUMAchine Multiprocessor''. [https://dblp.uni-trier.de/db/conf/icpp/icpp2000.html ICPP 2000], [http://www.eecg.toronto.edu/parallel/parallel/docs/icpp00.pdf pdf]
* [[Valavan Manohararajah]], [https://www.linkedin.com/in/terry-borer-501847/ Terry P. Borer], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2002'''). ''[https://www.semanticscholar.org/paper/Automatic-Partitioning-for-Improved-Placement-and-Manohararajah-Borer/d53ad046c377bedc4caa2f80dfc32339f0bc3d6d Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices]''. [https://dblp.uni-trier.de/db/conf/fpl/fpl2002.html FPL 2002]
* [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2003'''). ''[http://www.mhhe.com/engcs/electrical/brownvranesic/ Fundamentals of Digital Logic with Verilog Design]''. [http://catalogs.mhhe.com/mhhe/home.do McGraw-Hill]
* [[Valavan Manohararajah]], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2006'''). ''[https://ieeexplore.ieee.org/document/4100986/ Adaptive FPGAs: High-Level Architecture and a Synthesis Method]''. [https://dblp.uni-trier.de/db/conf/fpl/fpl2006.html FPL 2006], [http://www.eecg.toronto.edu/~brown/papers/fpl06-manohararajah.pdf pdf]
* [[Valavan Manohararajah]], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2006'''). ''[https://ieeexplore.ieee.org/document/1715419/ Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping].'' [[IEEE#TCICS|IEEE Transactions on CAD of Integrated Circuits and Systems]], Vol. 25, No. 11
* [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2007'''). ''[http://www.mhhe.com/engcs/electrical/brownvranesic/ Fundamentals of Digital Logic with Verilog Design]''. [http://catalogs.mhhe.com/mhhe/home.do McGraw-Hill], 2nd edition, [https://www.amazon.com/Fundamentals-Digital-Logic-Verilog-Design/dp/0077211642 amazon]
* [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2008'''). ''[http://www.mhhe.com/engcs/electrical/brownvranesic/ Fundamentals of Digital Logic with VHDL Design]''. [http://catalogs.mhhe.com/mhhe/home.do McGraw-Hill], 3rd edition, [https://www.amazon.com/Fundamentals-Digital-Logic-Design-CD-ROM/dp/0077221435/ref=dp_ob_title_bk amazon]
==2010 ...==
* [https://dblp.uni-trier.de/pers/hd/p/Plavec:Franjo Franjo Plavec], [[Zvonko Vranesic]], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown] ('''2013'''). ''[https://dl.acm.org/citation.cfm?id=2535932 Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs]''. [https://dblp.uni-trier.de/db/journals/trets/trets6.html TRETS], Vol. 6, No. 4
=External Links=
* [https://en.wikipedia.org/wiki/Zvonko_Vranesic Zvonko Vranesic from Wikipedia]
* [http://www.eecg.toronto.edu/%7Ezvonko/ Z.G. Vranesic homepage]
* [http://chess.ca/vranesic-zvonko Vranesic Zvonko | The Chess Federation of Canada - La Fédération Canadienne des Échecs]
* [http://www.chessgames.com/perl/chessplayer?pid=18958 The chess games of Dr. Zvonko Vranesic] from [http://www.chessgames.com/index.html chessgames.com]
* [http://www.croatia.org/crown/articles/10863/1/Zvonko-Vranesic-Croatian-Canadian-International-Chess-Master-and-Professor-at-the-University-of-Toronto.html Zvonko Vranesic Croatian-Canadian International Chess Master and Professor at the University of Toronto] by [https://en.wikipedia.org/wiki/Nenad_Bach Nenad N. Bach] and [https://www.fer.unizg.hr/en/darko.zubrinic Darko Žubrinić], [http://www.croatia.org/crown/ CROWN - Croatian World Network], July 09, 2016
* [https://ratings.fide.com/card.phtml?event=2600390 Vranesic, Zvonko FIDE Chess Profile]
=References=
<references />
'''[[People|Up one level]]'''
[[FILE:vranesic-zvonko.jpg|border|right|thumb|200px|link=http://www.croatia.org/crown/articles/10863/1/Zvonko-Vranesic-Croatian-Canadian-International-Chess-Master-and-Professor-at-the-University-of-Toronto.html| Zvonko Vranesic <ref>[http://www.croatia.org/crown/articles/10863/1/Zvonko-Vranesic-Croatian-Canadian-International-Chess-Master-and-Professor-at-the-University-of-Toronto.html Zvonko Vranesic Croatian-Canadian International Chess Master and Professor at the University of Toronto]</ref> ]]
'''Zvonko George Vranesic''',<br/>
a [https://en.wikipedia.org/wiki/Croatian_Canadians Croatian Canadian] chess and [https://en.wikipedia.org/wiki/Correspondence_Chess correspondence chess] [https://en.wikipedia.org/wiki/FIDE_titles#International_Master_.28IM.29 international master] <ref>[http://www.eecg.toronto.edu/%7Ezvonko/bio.html Biography - Z.G. Vranesic]</ref> , [https://en.wikipedia.org/wiki/Electrical_engineer electrical engineer], and [https://en.wikipedia.org/wiki/Professor_Emeritus professor emeritus] at Depature of Electrical and Computer Engineering, Computer Engineering Research Group, [[University of Toronto]]. His research interests covers [https://en.wikipedia.org/wiki/Multi-valued_logic Multiple-Valued Logic Systems], [https://en.wikipedia.org/wiki/Parallel_computing parallel computing] along with [[NUMA]], and [[FPGA]], beside other books on that topics, along with Stephen Brown <ref>[http://www.eecg.toronto.edu/%7Ebrown/ Professor Stephen Brown - University of Toronto]</ref>, he co-authored ''Fundamentals of Digital Logic'' with [https://en.wikipedia.org/wiki/VHDL VHDL] (2000) and [https://en.wikipedia.org/wiki/Verilog Verilog] Design.
=Chute=
In the 70s, along with his student [[Michael Valenti]], Zvonko Vranesic was co-author of [[Chute]] (CHess, University of Toronto, Engineering). He supervised Valenti's 1974 Masters Thesis <ref>[[Michael Valenti]] ('''1974'''). ''CHUTE I, An Easily Modifiable Chess Playing Program''. M.A.Sc. thesis, Depature of Electrical Engineering, [[University of Toronto]]</ref> , and co-authored ''Experiences with Chute'' after the [[WCCC 1977]] in the Proceedings of the 1977 annual [[ACM]] conference <ref>[[Michael Valenti]], [[Zvonko Vranesic]] ('''1977'''). ''[http://portal.acm.org/citation.cfm?id=810241 Experiences with CHUTE]''. Proceedings of the [[ACM]] conference</ref> .
=Chess Player=
Zvonko Vranesic represented Canada at five [https://en.wikipedia.org/wiki/Chess_Olympiad Chess Olympiads] <ref>[https://en.wikipedia.org/wiki/Zvonko_Vranesic#Olympiads Zvonko Vranesic - Olympiads]</ref> , he scored a [https://en.wikipedia.org/wiki/Grandmaster_%28chess%29 Grandmaster] norm at the [https://en.wikipedia.org/wiki/19th_Chess_Olympiad 19th Chess Olympiad] in [https://en.wikipedia.org/wiki/Siegen Siegen] <ref>[https://en.wikipedia.org/wiki/Zvonko_Vranesic Zvonko Vranesic from Wikipedia]</ref>. Notable are his wins against [https://en.wikipedia.org/wiki/Leonid_Stein Leonid Stein] at the [https://en.wikipedia.org/wiki/16th_Chess_Olympiad 16th Olympiad] in [https://en.wikipedia.org/wiki/Tel_Aviv Tel Aviv] 1964 <ref>[http://www.chessgames.com/perl/chessgame?gid=1132287, Dr. Zvonko Vranesic vs Leonid Stein] from [http://www.chessgames.com/index.html chessgames.com]
</ref>, and versus [[David Levy]] in [https://en.wikipedia.org/wiki/Lone_Pine,_California Lone Pine] 1975 <ref>[http://www.chessgames.com/perl/chessgame?gid=1434722, David Neil Lawrence Levy vs Dr. Zvonko Vranesic] from [http://www.chessgames.com/index.html chessgames.com]</ref> .
=Selected Games=
==Leonid Stein==
<pre>
[Event "Olympiad"]
[Site "Tel Aviv (Israel)"]
[Date "1964.??.??"]
[Round "?"]
[Result "1-0"]
[White "Dr. Zvonko Vranesic"]
[Black "Leonid Stein"]
1.d4 Nf6 2.c4 c5 3.d5 d6 4.Nc3 g6 5.e4 Bg7 6.Nf3 O-O 7.Be2 e6 8.O-O exd5 9.cxd5 Re8
10.Nd2 Na6 11.Re1 Nc7 12.Qc2 Rb8 13.a4 Na6 14.Bxa6 bxa6 15.Nc4 Rb4 16.Na2 Nxd5 17.Bd2 Rxc4
18.Qxc4 Nb6 19.Qc2 Qh4 20.Bc3 Bh6 21.Rad1 Nc4 22.Qe2 Be6 23.Nc1 Bf8 24.Nd3 Nb6 25.Qc2 Bd7
26.g3 Qg4 27.Nf4 Nxa4 28.Nd5 Re6 29.f3 Qg5 30.f4 Qd8 31.f5 gxf5 32.exf5 Rh6 33.Bd2 Rh5
34.Rf1 Bg7 35.Be3 Bc6 36.Qe4 Kh8 37.Qg4 Rh6 38.f6 Rxf6 39.Nxf6 Bxf6 40.Rxf6 Qxf6 41.Qc8+ Kg7
1-0
</pre>
==David Levy==
<pre>
[Event "Lone Pine"]
[Site "Lone Pine"]
[Date "1975.??.??"]
[Round "08"]
[Result "0-1"]
[White "David Neil Lawrence Levy"]
[Black "Dr. Zvonko Vranesic"]
1.e4 c5 2.Nf3 e6 3.d4 cxd4 4.Nxd4 Nc6 5.Nc3 d6 6.Bc4 Nf6 7.Be3 Be7 8.Qe2 a6 9.Bb3 O-O
10.O-O-O Qc7 11.Kb1 Nxd4 12.Bxd4 b5 13.e5 dxe5 14.Bxe5 Qc6 15.f3 Bb7 16.Rd4 Rfd8
17.Rhd1 Rxd4 18.Rxd4 Rd8 19.Rxd8+ Bxd8 20.Qd3 Be7 21.Qd4 Qc5 22.Ne2 Qxd4 23.Bxd4 Bd6
24.h3 e5 25.Be3 e4 26.f4 Nd5 27.Bxd5 Bxd5 28.b3 f5 29.Kb2 Kf7 30.Kc3 g6 31.Kd4 Ke6
32.Kc3 Bb7 33.Nd4+ Kd5 34.b4 Bc8 35.h4 Be7 36.g3 Bf6 37.a3 Be6 38.Bg1 h6 39.Be3 Bf7
40.Bg1 g5 41.hxg5 hxg5 42.fxg5 Be5 43.Bf2 Bg6 44.Be3 Bxg3 45.Ne2 Be5+ 46.Kb3 Bh5
0-1
</pre>
=Selected Publications=
<ref>[https://dblp.uni-trier.de/pers/hd/v/Vranesic:Zvonko_G= dblp: Zvonko G. Vranesic]</ref>
==1970 ...==
* [[Zvonko Vranesic]], [https://www.ece.utoronto.ca/news/e-s-lee-tribute/ E. Stewart Lee], [https://en.wikipedia.org/wiki/Kenneth_C._Smith Kenneth C. Smith] ('''1970'''). ''A Many-Valued Algebra for Switching Systems''. [[IEEE#TOC|IEEE Transactions on Computers]], Vol. 19, No. 10
* [[Zvonko Vranesic]], [https://en.wikipedia.org/wiki/Kenneth_C._Smith Kenneth C. Smith] ('''1974'''). ''Engineering aspects of multi-valued logic systems''. [[IEEE#TOC|IEEE Transactions on Computers]], Vol. 7, No. 9
* [[Michael Valenti]], [[Zvonko Vranesic]] ('''1977'''). ''[http://portal.acm.org/citation.cfm?id=810241 Experiences with CHUTE]''. [[ACM]] conference
* [[Zvonko Vranesic]] ('''1977'''). ''Multiple-Valued Logic: An Introduction and Overview''. [[IEEE#TOC|IEEE Transactions on Computers]], Vol. 26, No. 12
==1980 ...==
* [https://en.wikipedia.org/wiki/Hussein_T._Mouftah Hussein T. Mouftah], [https://en.wikipedia.org/wiki/Kenneth_C._Smith Kenneth C. Smith], [[Zvonko Vranesic]] ('''1980'''). ''Ternary Rate-Multipliers''. [[IEEE#TOC|IEEE Transactions on Computers]], Vol. 29, No. 10
* [https://dblp.uni-trier.de/pers/hd/r/Rose:Jonathan Jonathan Rose], [https://dblp.uni-trier.de/pers/hd/l/Loucks:Wayne_M= Wayne M. Loucks], [[Zvonko Vranesic]] ('''1985'''). ''[https://ieeexplore.ieee.org/document/4089459/ FERMTOR: A Tunable Multiprocessor Architecture]''. [[IEEE#Micro|IEEE Micro]], Vol. 5, No. 4
* [https://dblp.uni-trier.de/pers/hd/r/Rose:Jonathan Jonathan Rose], [https://dblp.uni-trier.de/pers/hd/s/Snelgrove:W=_Martin W. Martin Snelgrove], [[Zvonko Vranesic]] ('''1988'''). ''[https://ieeexplore.ieee.org/document/3172/ Parallel standard cell placement algorithms with quality equivalent to simulated annealing]''. [[IEEE#TCICS|IEEE Transactions on CAD of Integrated Circuits and Systems]], Vol. 7, No. 3
==1990 ...==
* [[Zeljko Zilic]], [[Zvonko Vranesic]] ('''1993'''). ''[https://ieeexplore.ieee.org/document/289552/ Current-Mode CMOS Galois Field Circuits]''. [https://dblp.uni-trier.de/db/conf/ismvl/ismvl1993.html ISMVL 1993]
* [[Zeljko Zilic]], [[Zvonko Vranesic]] ('''1995'''). ''[https://ieeexplore.ieee.org/document/403717/ A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions]''. [[IEEE#TOC|IEEE Transactions on Computers]], Vol. 44, No. 8 <ref>[https://en.wikipedia.org/wiki/Reed%E2%80%93Muller_code Reed–Muller code from Wikipedia]</ref>
* [[Zeljko Zilic]], [[Zvonko Vranesic]] ('''1996'''). ''[https://www.computer.org/csdl/proceedings/fpga/1996/2576/00/25760024-abs.html Using BDDs to Design ULMs for FPGAs]''. [https://dblp.uni-trier.de/db/conf/fpga/fpga96.html FPGA 1996]
* [[Zvonko Vranesic]] ('''1998'''). ''[https://ieeexplore.ieee.org/document/679318/ The FPGA Challenge]''. [https://dblp.uni-trier.de/db/conf/ismvl/ismvl1998.html ISMVL 1998]
* [https://www.linkedin.com/in/ante-grbi%C4%87-0657665b/ Ante Grbić], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [https://dblp.uni-trier.de/pers/hd/c/Caranci:S= Steve Caranci], [https://www.linkedin.com/in/robin-grindley-47550/ Robin Grindley], [https://dblp.uni-trier.de/pers/hd/g/Gusat:Mitchell Mitchell Gusat], [http://www.ece.ubc.ca/~lemieux/ Guy Lemieux], [https://dblp.uni-trier.de/pers/hd/l/Loveless:K= K. Loveless], [https://dblp.uni-trier.de/pers/hd/m/Manjikian:Naraig Naraig Manjikian], [https://www.linkedin.com/in/sinisasrbljic/ Sinisa Srbljic], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=67137 Michael Stumm], [[Zvonko Vranesic]], [[Zeljko Zilic]] ('''1998'''). ''[https://ieeexplore.ieee.org/document/724441/ Design and Implementation of the NUMAchine Multiprocessor]''. [https://dblp.uni-trier.de/db/conf/dac/dac98.html DAC 1998], [http://www.eecg.toronto.edu/parallel/parallel/docs/dac98.pdf pdf] <ref>[http://www.eecg.toronto.edu/parallel/parallel/numadocs.html Documentation on the NUMAchine Multiprocessor]</ref>
* [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''1999'''). ''[http://www.mhhe.com/engcs/electrical/brownvranesic/ Fundamentals of Digital Logic with VHDL Design]''. [http://catalogs.mhhe.com/mhhe/home.do McGraw-Hill]
==2000 ...==
* [https://www.linkedin.com/in/robin-grindley-47550/ Robin Grindley], [http://www.eecg.toronto.edu/~tsa/ Tarek Abdelrahman], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [https://dblp.uni-trier.de/pers/hd/c/Caranci:S= Steve Caranci], [https://dblp.uni-trier.de/pers/hd/d/DeVries:D= D. DeVries], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=67177 Benjamin Gamsa], [https://www.linkedin.com/in/ante-grbi%C4%87-0657665b/ Ante Grbić], [https://dblp.uni-trier.de/pers/hd/g/Gusat:Mitchell Mitchell Gusat], [https://dblp.uni-trier.de/pers/hd/h/Ho:R= R. Ho], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=99397 Orran Krieger], [http://www.ece.ubc.ca/~lemieux/ Guy Lemieux], [https://dblp.uni-trier.de/pers/hd/l/Loveless:K= K. Loveless], [https://dblp.uni-trier.de/pers/hd/m/Manjikian:Naraig Naraig Manjikian], [https://dblp.uni-trier.de/pers/hd/m/McHardy:P= P. McHardy], [https://www.linkedin.com/in/sinisasrbljic/ Sinisa Srbljic], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=67137 Michael Stumm], [[Zvonko Vranesic]], [[Zeljko Zilic]] ('''2000'''). ''The NUMAchine Multiprocessor''. [https://dblp.uni-trier.de/db/conf/icpp/icpp2000.html ICPP 2000], [http://www.eecg.toronto.edu/parallel/parallel/docs/icpp00.pdf pdf]
* [[Valavan Manohararajah]], [https://www.linkedin.com/in/terry-borer-501847/ Terry P. Borer], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2002'''). ''[https://www.semanticscholar.org/paper/Automatic-Partitioning-for-Improved-Placement-and-Manohararajah-Borer/d53ad046c377bedc4caa2f80dfc32339f0bc3d6d Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices]''. [https://dblp.uni-trier.de/db/conf/fpl/fpl2002.html FPL 2002]
* [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2003'''). ''[http://www.mhhe.com/engcs/electrical/brownvranesic/ Fundamentals of Digital Logic with Verilog Design]''. [http://catalogs.mhhe.com/mhhe/home.do McGraw-Hill]
* [[Valavan Manohararajah]], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2006'''). ''[https://ieeexplore.ieee.org/document/4100986/ Adaptive FPGAs: High-Level Architecture and a Synthesis Method]''. [https://dblp.uni-trier.de/db/conf/fpl/fpl2006.html FPL 2006], [http://www.eecg.toronto.edu/~brown/papers/fpl06-manohararajah.pdf pdf]
* [[Valavan Manohararajah]], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2006'''). ''[https://ieeexplore.ieee.org/document/1715419/ Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping].'' [[IEEE#TCICS|IEEE Transactions on CAD of Integrated Circuits and Systems]], Vol. 25, No. 11
* [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2007'''). ''[http://www.mhhe.com/engcs/electrical/brownvranesic/ Fundamentals of Digital Logic with Verilog Design]''. [http://catalogs.mhhe.com/mhhe/home.do McGraw-Hill], 2nd edition, [https://www.amazon.com/Fundamentals-Digital-Logic-Verilog-Design/dp/0077211642 amazon]
* [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [[Zvonko Vranesic]] ('''2008'''). ''[http://www.mhhe.com/engcs/electrical/brownvranesic/ Fundamentals of Digital Logic with VHDL Design]''. [http://catalogs.mhhe.com/mhhe/home.do McGraw-Hill], 3rd edition, [https://www.amazon.com/Fundamentals-Digital-Logic-Design-CD-ROM/dp/0077221435/ref=dp_ob_title_bk amazon]
==2010 ...==
* [https://dblp.uni-trier.de/pers/hd/p/Plavec:Franjo Franjo Plavec], [[Zvonko Vranesic]], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown] ('''2013'''). ''[https://dl.acm.org/citation.cfm?id=2535932 Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs]''. [https://dblp.uni-trier.de/db/journals/trets/trets6.html TRETS], Vol. 6, No. 4
=External Links=
* [https://en.wikipedia.org/wiki/Zvonko_Vranesic Zvonko Vranesic from Wikipedia]
* [http://www.eecg.toronto.edu/%7Ezvonko/ Z.G. Vranesic homepage]
* [http://chess.ca/vranesic-zvonko Vranesic Zvonko | The Chess Federation of Canada - La Fédération Canadienne des Échecs]
* [http://www.chessgames.com/perl/chessplayer?pid=18958 The chess games of Dr. Zvonko Vranesic] from [http://www.chessgames.com/index.html chessgames.com]
* [http://www.croatia.org/crown/articles/10863/1/Zvonko-Vranesic-Croatian-Canadian-International-Chess-Master-and-Professor-at-the-University-of-Toronto.html Zvonko Vranesic Croatian-Canadian International Chess Master and Professor at the University of Toronto] by [https://en.wikipedia.org/wiki/Nenad_Bach Nenad N. Bach] and [https://www.fer.unizg.hr/en/darko.zubrinic Darko Žubrinić], [http://www.croatia.org/crown/ CROWN - Croatian World Network], July 09, 2016
* [https://ratings.fide.com/card.phtml?event=2600390 Vranesic, Zvonko FIDE Chess Profile]
=References=
<references />
'''[[People|Up one level]]'''
