Difference between revisions of "Talk:GPU"

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(embedded CPU controller)
(Nvidia architectures: new section)
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== Nvidia architectures ==
  
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Afaik Nvidia did never official mention SIMD in their papers as hardware architecture, with Tesla they only referred to as SIMT.
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Nevertheless, my own conclusions are:
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Tesla has 8 wide SIMD, executing a Warp of 32 threads over 4 cycles.
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Fermi has 16 wide SIMD, executing a Warp of 32 threads over 2 cycles.
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Kepler is somehow odd, not sure how the compute units are partitioned.
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Maxwell and Pascal have 32 wide SIMD, executing a Warp of 32 threads over 1 cycle.
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Volta and Turing seem to have 16 wide FPU SIMDs, but my own experiments show 32 wide VALU.

Revision as of 11:45, 18 April 2021

Nvidia architectures

Afaik Nvidia did never official mention SIMD in their papers as hardware architecture, with Tesla they only referred to as SIMT.

Nevertheless, my own conclusions are:

Tesla has 8 wide SIMD, executing a Warp of 32 threads over 4 cycles.

Fermi has 16 wide SIMD, executing a Warp of 32 threads over 2 cycles.

Kepler is somehow odd, not sure how the compute units are partitioned.

Maxwell and Pascal have 32 wide SIMD, executing a Warp of 32 threads over 1 cycle.

Volta and Turing seem to have 16 wide FPU SIMDs, but my own experiments show 32 wide VALU.