SSE5
Streaming SIMD Extensions version 5 (SSE5),
was a x86-64 SIMD instruction set extension proposed by AMD in 2007, with a bunch of very interesting instructions for high performance bitboarding and evaluation. However, after Intel declared their 256-bit wide Advanced Vector Extensions (AVX) as further SIMD extension, AMD reconsidered and replaced SSE5 with three smaller instruction set extensions XOP for vectors of integers, FMA4 (fused multiply-add on vectors of float and double), and CVT16 (Half precision floating-point format), which retain the proposed functionality of SSE5, but encode the instructions differently for better compatibility with Intel's proposed AVX instruction set and the new VEX prefix coding scheme. The sets are stated for introduction in AMD's new Bulldozer processor core, due for release in late 2011 on a 32nm process [1] .
Instructions
Some of the new instructions are quite interesting for computer chess, with applications in evaluation and byte shuffling of bitboards. Their XOP successors still work on 128-bit XMM registers [2], and implicitly clear the upper 128 bit of a 256-bit YMM register. Some of the instructions, like VPPERM, have as many as 4 operands.
See Also
External Links
References
- ↑ AMD Fusion now pushed back to 2011 by Joel Hruska, November 14, 2008
- ↑ Volume 6: 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions (pdf)
