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* [[AltiVec]] on [[PowerPC#G4|PowerPC G4]], [[PowerPC#G5|PowerPC G5]]
* [[ARM NEON]]
* [[ARM Helium]]
* [[AVX]] by [[Intel]]
* [[AVX2]] by [[Intel]]
=See also=
* [[GPU]]
* [[NNUE]]
* [[Parallel Prefix Algorithms]]
==2020 ...==
* [http://www.talkchess.com/forum3/viewtopic.php?f=7&t=73126 SIMD methods in TT probing and replacement] by [[Harm Geert Muller]], [[CCC]], February 20, 2020 » [[Transposition Table]]
* [http://www.talkchess.com/forum3/viewtopic.php?f=2&t=75862 CPU Vector Unit, the new jam for NNs...] by [[Srdja Matovic]], [[CCC]], November 18, 2020 » [[NNUE]]
=External Links=
* [https://en.wikipedia.org/wiki/SWAR SWAR from Wikipedia]
* [http://www.aggregate.org/SWAR/ The Aggregate: SWAR, SIMD Within A Register] by [[Hank Dietz]]
==[[x86]]/[[x86-64]]==
* [https://en.wikipedia.org/wiki/MMX_%28instruction_set%29 MMX from Wikipedia]
* [https://en.wikipedia.org/wiki/3DNow 3DNow! from Wikipedia]
* [http://sseplus.sourceforge.net/index.html SSEPlus Project Documentation]
==Other==
* [httphttps://wwwdeveloper.arm.com/productsarchitectures/multimediainstruction-sets/simd-isas/neon/index.html ARM NEON TechnologySIMD ISAs | Neon – Arm Developer]
* [https://en.wikipedia.org/wiki/ARM_architecture#Advanced_SIMD_.28NEON.29 ARM NEON Technology from Wikipedia]
* [https://developer.arm.com/architectures/instruction-sets/simd-isas/helium SIMD ISAs | Arm Helium technology – Arm Developer]
* [https://en.wikipedia.org/wiki/AltiVec AltiVec from Wikipedia]
==Misc==
* [https://en.wikipedia.org/wiki/Explicitly_parallel_instruction_computing Explicitly parallel instruction computing (EPIC) from Wikipedia]
