Difference between revisions of "NUMA"

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(Created page with "'''Home * Hardware * Memory * NUMA''' FILE:NUMA.svg|border|right|thumb| Possible NUMA system <ref>One possible architecture of a NUMA system. Original...")
 
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=Selected Publications=
 
=Selected Publications=
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==1998 ...==
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* [https://www.linkedin.com/in/ante-grbi%C4%87-0657665b/ Ante Grbić], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [https://dblp.uni-trier.de/pers/hd/c/Caranci:S= Steve Caranci], [https://www.linkedin.com/in/robin-grindley-47550/ Robin Grindley], [https://dblp.uni-trier.de/pers/hd/g/Gusat:Mitchell Mitchell Gusat], [http://www.ece.ubc.ca/~lemieux/ Guy Lemieux], [https://dblp.uni-trier.de/pers/hd/l/Loveless:K= K. Loveless], [https://dblp.uni-trier.de/pers/hd/m/Manjikian:Naraig Naraig Manjikian], [https://www.linkedin.com/in/sinisasrbljic/ Sinisa Srbljic], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=67137 Michael Stumm], [[Zvonko Vranesic]], [[Zeljko Zilic]] ('''1998'''). ''[https://ieeexplore.ieee.org/document/724441/ Design and Implementation of the NUMAchine Multiprocessor]''. [https://dblp.uni-trier.de/db/conf/dac/dac98.html DAC 1998], [http://www.eecg.toronto.edu/parallel/parallel/docs/dac98.pdf pdf] <ref>[http://www.eecg.toronto.edu/parallel/parallel/numadocs.html Documentation on the NUMAchine Multiprocessor]</ref>
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==2000 ...==
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* [https://www.linkedin.com/in/robin-grindley-47550/ Robin Grindley], [http://www.eecg.toronto.edu/~tsa/ Tarek Abdelrahman], [http://www.eecg.toronto.edu/%7Ebrown/ Stephen Brown], [https://dblp.uni-trier.de/pers/hd/c/Caranci:S= Steve Caranci], [https://dblp.uni-trier.de/pers/hd/d/DeVries:D= D. DeVries], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=67177 Benjamin Gamsa], [https://www.linkedin.com/in/ante-grbi%C4%87-0657665b/ Ante Grbić], [https://dblp.uni-trier.de/pers/hd/g/Gusat:Mitchell Mitchell Gusat], [https://dblp.uni-trier.de/pers/hd/h/Ho:R= R. Ho], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=99397 Orran Krieger], [http://www.ece.ubc.ca/~lemieux/ Guy Lemieux], [https://dblp.uni-trier.de/pers/hd/l/Loveless:K= K. Loveless], [https://dblp.uni-trier.de/pers/hd/m/Manjikian:Naraig Naraig Manjikian], [https://dblp.uni-trier.de/pers/hd/m/McHardy:P= P. McHardy], [https://www.linkedin.com/in/sinisasrbljic/ Sinisa Srbljic], [https://www.genealogy.math.ndsu.nodak.edu/id.php?id=67137 Michael Stumm], [[Zvonko Vranesic]], [[Zeljko Zilic]] ('''2000'''). ''The NUMAchine Multiprocessor''. [https://dblp.uni-trier.de/db/conf/icpp/icpp2000.html ICPP 2000], [http://www.eecg.toronto.edu/parallel/parallel/docs/icpp00.pdf pdf]
 
* [http://www.halobates.de/ Andi Kleen] ('''2004'''). ''An NUMA API for Linux''. SUSE Labs, [http://halobates.de/numaapi3.pdf pdf]
 
* [http://www.halobates.de/ Andi Kleen] ('''2004'''). ''An NUMA API for Linux''. SUSE Labs, [http://halobates.de/numaapi3.pdf pdf]
 
* [http://de.wikipedia.org/wiki/Ulrich_Drepper Ulrich Drepper] ('''2007'''). ''What Every Programmer Should Know About Memory''. [http://www.akkadia.org/drepper/cpumemory.pdf pdf], also hosted by [https://en.wikipedia.org/wiki/LWN.net LWN.net]
 
* [http://de.wikipedia.org/wiki/Ulrich_Drepper Ulrich Drepper] ('''2007'''). ''What Every Programmer Should Know About Memory''. [http://www.akkadia.org/drepper/cpumemory.pdf pdf], also hosted by [https://en.wikipedia.org/wiki/LWN.net LWN.net]
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* [http://lwn.net/Articles/254445/ Memory part 4: NUMA support]
 
* [http://lwn.net/Articles/254445/ Memory part 4: NUMA support]
 
: [http://lwn.net/Articles/255364/ Memory part 5: What programmers can do]
 
: [http://lwn.net/Articles/255364/ Memory part 5: What programmers can do]
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==2010 ...==
 
* [https://www.linkedin.com/in/nakulmanchanda Nakul Manchanda], [https://www.linkedin.com/in/anandkaran Karan Anand] ('''2010'''). ''Non-Uniform Memory Access (NUMA)''. [https://en.wikipedia.org/wiki/New_York_University New York University], [http://cs.nyu.edu/~lerner/spring10/projects/NUMA.pdf pdf]
 
* [https://www.linkedin.com/in/nakulmanchanda Nakul Manchanda], [https://www.linkedin.com/in/anandkaran Karan Anand] ('''2010'''). ''Non-Uniform Memory Access (NUMA)''. [https://en.wikipedia.org/wiki/New_York_University New York University], [http://cs.nyu.edu/~lerner/spring10/projects/NUMA.pdf pdf]
 
* [https://scholar.google.de/citations?user=wx0D5q0AAAAJ&hl=en Stefan Lankes], [https://www.researchgate.net/profile/Thomas_Roehl Thomas Roehl], [https://terboven.com/ Christian Terboven], [https://www.linkedin.com/in/thomas-bemmerl-b3657547 Thomas Bemmerl] ('''2012'''). ''[http://publications.rwth-aachen.de/record/207349 Node-Based Memory Management for Scalable NUMA Architectures]''. [https://en.wikipedia.org/wiki/RWTH_Aachen_University RWTH Aachen], [http://www.mcs.anl.gov/events/workshops/ross/2012/ ROSS 2012], [http://htor.inf.ethz.ch/ross2012/slides/ross2012-lankes.pdf slides as pdf]  
 
* [https://scholar.google.de/citations?user=wx0D5q0AAAAJ&hl=en Stefan Lankes], [https://www.researchgate.net/profile/Thomas_Roehl Thomas Roehl], [https://terboven.com/ Christian Terboven], [https://www.linkedin.com/in/thomas-bemmerl-b3657547 Thomas Bemmerl] ('''2012'''). ''[http://publications.rwth-aachen.de/record/207349 Node-Based Memory Management for Scalable NUMA Architectures]''. [https://en.wikipedia.org/wiki/RWTH_Aachen_University RWTH Aachen], [http://www.mcs.anl.gov/events/workshops/ross/2012/ ROSS 2012], [http://htor.inf.ethz.ch/ross2012/slides/ross2012-lankes.pdf slides as pdf]  

Revision as of 10:25, 17 June 2018

Home * Hardware * Memory * NUMA

Possible NUMA system [1]

NUMA, (Non-uniform memory access)
a multiprocessing memory design where the main memory is partitioned between processors. Opposed to SMP, where all processors compete for access to the centralized shared memory bus, making it difficult to scale well bejoind 8 to 12 CPUs [2], NUMA splits the main memory into so called nodes with separate memory busses for subsets of processors, and high speed interconnection between nodes, either directly in so called 1-hop distance, or indirectly in 2-hop distance. Despite the high speed interconnection, NUMA memory access time varies considerably between faster local memory and remote memory of other nodes. Maintaining cache coherence of processor caches adds significant overhead to NUMA Systems, addressed by ccNUMA which is mostly used synonymous for current NUMA implementations [3].

x86

AMD implemented NUMA with its Opteron processor in 2003, using HyperTransport. Intel announced NUMA compatibility for their x86 servers in late 2007 with Nehalem CPUs using QuickPath Interconnect [4].

Considerations

Scheduling of threads across nodes and cores of a system is a complicated topic due to access of independent or shared data. There are several considerations in ccNUMA aware operating systems and software, such as keeping data local by virtue of first touch [5] [6]. NUMA and processor affinity APIs help application programmers to bind threads or processes to NUMA nodes or to allocate memory from a certain node.

See also

Selected Publications

1998 ...

2000 ...

Memory part 1
Memory part 2: CPU caches
Memory part 3: Virtual Memory
Memory part 5: What programmers can do

2010 ...

Forum Posts

2000 ...

2010 ...

2015 ...

Re: thread affinity by Robert Hyatt, CCC, July 03, 2015

External Links

Linux

Windows

x86

References

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