Changes

[https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory] (DRAM) is a type of random access memory that stores each bit of data in a separate [https://en.wikipedia.org/wiki/Capacitor capacitor] within an electronic circuit. Since capacitors leak charge, the information eventually fades unless the capacitor charge is [https://en.wikipedia.org/wiki/Memory_refresh refreshed] periodically, which is the reason to call that memory dynamic. Since DRAM takes only one [https://en.wikipedia.org/wiki/Transistor transistor] and capacitor per bit, it is therefor used as cheap main memory part of recent [https://en.wikipedia.org/wiki/Computer_data_storage computer data storage], despite its worse latency compared to SRAM.

* [https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory from Wikipedia]

* [https://en.wikipedia.org/wiki/Interleaved_memory Interleaved memory]

* [https://en.wikipedia.org/wiki/SDRAM_latency SDRAM latency]

Since each data-bit stored in a ROM is a boolean function of its inputs or address, a ROM is also used to implement [[Combinatorial Logic|combinatorial logic]].

* [https://en.wikipedia.org/wiki/Read-only_memory Read-only memory from Wikipedia]

=Auxiliary Storage=

* [[Dennis Breuker]] ('''1998'''). ''Memory versus Search in Games''. Ph.D. thesis, [[Maastricht University]], pdf available via [http://www.dennisbreuker.nl/thesis/index.html Dennis Breuker's page]

* [[Harald Prokop]] ('''1999'''). ''Cache-Oblivious Algorithms''. Masters thesis, Department of Electrical Engineering and Computer Science, [[Massachusetts Institute of Technology|MIT]], [http://supertech.csail.mit.edu/papers/Prokop99.pdf pdf] <ref>[https://en.wikipedia.org/wiki/Cache-oblivious_algorithm Cache-oblivious algorithm from Wikipedia]</ref>

===2000 ...===

* [http://dblp.uni-trier.de/pers/hd/y/Yang:Yue Yue Yang], [http://dblp.uni-trier.de/pers/hd/g/Gopalakrishnan:Ganesh Ganesh Gopalakrishnan], [[Gary Lindstrom]] ('''2002'''). ''Specifying Java Thread Semantics Using a Uniform Memory Model''. [http://dblp.uni-trier.de/db/conf/java/java2002.html#YangGL02 Java Grande 2002], [http://formalverification.cs.utah.edu/yyang/papers/umm_old.pdf pdf]

: [http://lwn.net/Articles/254445/ Memory part 4: NUMA support]

: [http://lwn.net/Articles/255364/ Memory part 5: What programmers can do]

* [[David Silver]], [[Richard Sutton]], [[Martin Müller]] ('''2008'''). ''Sample-Based Learning and Search with Permanent and Transient Memories''. In Proceedings of the 25th International Conference on Machine Learning, [http://webdocs.cs.ualberta.ca/%7Esilver/David_Silver/Publications_files/dyna2.pdf pdf]

===2010 ...===

===1980 ...===

* [[Marvin Minsky]] ('''1980'''). ''K-Lines: A Theory of Memory''. Cognitive Science 4, 117-133, [http://csjarchive.cogsci.rpi.edu/1980v04/i02/p0117p0133/MAIN.PDF pdf] <ref>[https://en.wikipedia.org/wiki/K-line_%28artificial_intelligence%29 K-line (artificial intelligence) from Wikipedia]</ref>

* [[A. Harry Klopf]] ('''1982'''). ''The Hedonistic Neuron: A Theory of Memory, Learning, and Intelligence''. Hemisphere Publishing Corporation, [[University of Michigan]]

===1990 ...===

* [http://www.talkchess.com/forum/viewtopic.php?t=38441 MSVC calloc question] by [[Harm Geert Muller]], [[CCC]], March 17, 2011

'''2012'''

* [http://www.talkchess.com/forum/viewtopic.php?t=44826 DNA data storage breaks records] by Terry McCracken, [[CCC]], August 18, 2012 <ref>[https://en.wikipedia.org/wiki/George_Church George Church], [http://www.bme.jhu.edu/people/primary.php?id=1045 Yuan Gao], [http://openwetware.org/wiki/Sriram_Kosuri Sriram Kosuri] ('''2012'''). ''[http://www.sciencemag.org/content/early/2012/08/15/science.1226355 Next-Generation Digital Information Storage in DNA]''. [https://en.wikipedia.org/wiki/Science_%28journal%29 Science]</ref>

'''2013'''

* [http://www.talkchess.com/forum/viewtopic.php?t=61472 What do you do with NUMA?] by [[Matthew Lai]], [[CCC]], September 19, 2016 » [[NUMA]]

* [http://rybkaforum.net/cgi-bin/rybkaforum/topic_show.pl?tid=31867 L3 cache, RAM and other performance factors] by Nimzy, [[Computer Chess Forums|Rybka Forum]], December 04, 2016 » [[Playing Strength]]

* [http://www.talkchess.com/forum/viewtopic.php?t=63652 6-men Syzygy from HDD and USB 3.0] by [[Kai Laskos]], [[CCC]], April 04, 2017 » [[Komodo]], [[Playing Strength]], [[Syzygy Bases]], [[Memory#USB3|USB 3.0]]

* [http://www.talkchess.com/forum/viewtopic.php?t=63886 RAM speed and engine strength] by John Hartmann, [[CCC]], May 03, 2017 » [[Memory#RAM|RAM]], [[Playing Strength]]

=External Links=