Difference between revisions of "Memory"

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[https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory] (DRAM) is a type of random access memory that stores each bit of data in a separate [https://en.wikipedia.org/wiki/Capacitor capacitor] within an electronic circuit. Since capacitors leak charge, the information eventually fades unless the capacitor charge is [https://en.wikipedia.org/wiki/Memory_refresh refreshed] periodically, which is the reason to call that memory dynamic. Since DRAM takes only one [https://en.wikipedia.org/wiki/Transistor transistor] and capacitor per bit, it is therefor used as cheap main memory part of recent [https://en.wikipedia.org/wiki/Computer_data_storage computer data storage], despite its worse latency compared to SRAM.
 
[https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory] (DRAM) is a type of random access memory that stores each bit of data in a separate [https://en.wikipedia.org/wiki/Capacitor capacitor] within an electronic circuit. Since capacitors leak charge, the information eventually fades unless the capacitor charge is [https://en.wikipedia.org/wiki/Memory_refresh refreshed] periodically, which is the reason to call that memory dynamic. Since DRAM takes only one [https://en.wikipedia.org/wiki/Transistor transistor] and capacitor per bit, it is therefor used as cheap main memory part of recent [https://en.wikipedia.org/wiki/Computer_data_storage computer data storage], despite its worse latency compared to SRAM.
 
* [https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory from Wikipedia]
 
* [https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory from Wikipedia]
: [https://en.wikipedia.org/wiki/SDRAM Synchronous dynamic random access memory (SDRAM)]
+
* [https://en.wikipedia.org/wiki/SDRAM Synchronous dynamic random access memory (SDRAM)]
: [https://en.wikipedia.org/wiki/DDR_SDRAM DDR SDRAM] with [https://en.wikipedia.org/wiki/Double_data_rate Double data rate]
+
* [https://en.wikipedia.org/wiki/DDR_SDRAM DDR SDRAM] with [https://en.wikipedia.org/wiki/Double_data_rate Double data rate]
 +
** <span id="DDR2"></span>[https://en.wikipedia.org/wiki/DDR2_SDRAM DDR2 SDRAM]
 +
** <span id="DDR3"></span>[https://en.wikipedia.org/wiki/DDR3_SDRAM DDR3 SDRAM]
 +
** <span id="DDR4"></span>[https://en.wikipedia.org/wiki/DDR4_SDRAM DDR4 SDRAM]
 +
** <span id="DDR5"></span>[https://en.wikipedia.org/wiki/DDR5_SDRAM DDR5 SDRAM]
 
* [https://en.wikipedia.org/wiki/Interleaved_memory Interleaved memory]
 
* [https://en.wikipedia.org/wiki/Interleaved_memory Interleaved memory]
 
* [https://en.wikipedia.org/wiki/SDRAM_latency SDRAM latency]
 
* [https://en.wikipedia.org/wiki/SDRAM_latency SDRAM latency]
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Since each data-bit stored in a ROM is a boolean function of its inputs or address, a ROM is also used to implement [[Combinatorial Logic|combinatorial logic]].
 
Since each data-bit stored in a ROM is a boolean function of its inputs or address, a ROM is also used to implement [[Combinatorial Logic|combinatorial logic]].
 
* [https://en.wikipedia.org/wiki/Read-only_memory Read-only memory from Wikipedia]
 
* [https://en.wikipedia.org/wiki/Read-only_memory Read-only memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Non-volatile_memory Non-volatile memory from Wikipedia]
+
 
 +
=Persistence=
 +
* [https://en.wikipedia.org/wiki/Persistence_(computer_science) Persistence]
 +
* [https://en.wikipedia.org/wiki/Non-volatile_memory Non-volatile memory]
 +
* [https://en.wikipedia.org/wiki/Non-volatile_random-access_memory Non-volatile random-access memory]
 +
* [https://en.wikipedia.org/wiki/Persistent_memory Persistent memory]
  
 
=Auxiliary Storage=  
 
=Auxiliary Storage=  
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* [https://en.wikipedia.org/wiki/False_sharing False sharing from Wikipedia]
 
* [https://en.wikipedia.org/wiki/False_sharing False sharing from Wikipedia]
 
* [https://en.wikipedia.org/wiki/Miles_Davis_Quintet Miles Davis Quintet] - [https://en.wikipedia.org/wiki/Footprints_(composition) Footprints]  ([[:Category:Wayne Shorter|Wayne Shorter]]), New York, 1966, [https://en.wikipedia.org/wiki/YouTube YouTube] Video
 
* [https://en.wikipedia.org/wiki/Miles_Davis_Quintet Miles Davis Quintet] - [https://en.wikipedia.org/wiki/Footprints_(composition) Footprints]  ([[:Category:Wayne Shorter|Wayne Shorter]]), New York, 1966, [https://en.wikipedia.org/wiki/YouTube YouTube] Video
: [[:Category:Miles Davis|Miles Davis]], [[:Category:Wayne Shorter|Wayne Shorter]], [[:Category:Herbie Hancock|Herbie Hancock]], [https://en.wikipedia.org/wiki/Ron_Carter Ron Carter], [https://en.wikipedia.org/wiki/Tony_Williams_(drummer) Tony Williams]
+
: [[:Category:Miles Davis|Miles Davis]], [[:Category:Wayne Shorter|Wayne Shorter]], [[:Category:Herbie Hancock|Herbie Hancock]], [[:Category:Ron Carter|Ron Carter]], [https://en.wikipedia.org/wiki/Tony_Williams_(drummer) Tony Williams]
 
: {{#evu:https://www.youtube.com/watch?v=j7lkqxfvA78|alignment=left|valignment=top}}
 
: {{#evu:https://www.youtube.com/watch?v=j7lkqxfvA78|alignment=left|valignment=top}}
 
* [http://krakowskascenamuzyczna.pl/tag/monika-malczak/ Monika Malczak Quartet] - [https://en.wikipedia.org/wiki/Footprints_(composition) Footprints], [http://www2.polskieradio.pl/studio/lutoslawski_en.aspx Witold Lutosławski Concert Studio of Polish Radio], [https://en.wikipedia.org/wiki/Warsaw Warsaw], May 20, 2016, [https://en.wikipedia.org/wiki/YouTube YouTube] Video
 
* [http://krakowskascenamuzyczna.pl/tag/monika-malczak/ Monika Malczak Quartet] - [https://en.wikipedia.org/wiki/Footprints_(composition) Footprints], [http://www2.polskieradio.pl/studio/lutoslawski_en.aspx Witold Lutosławski Concert Studio of Polish Radio], [https://en.wikipedia.org/wiki/Warsaw Warsaw], May 20, 2016, [https://en.wikipedia.org/wiki/YouTube YouTube] Video
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* [[Wim Pijls]], [[Arie de Bruin]] ('''1993'''). ''SSS*-like Algorithms in Constrained Memory.'' [[ICGA Journal#16_1|ICCA Journal, Vol. 16, No. 1]]
 
* [[Wim Pijls]], [[Arie de Bruin]] ('''1993'''). ''SSS*-like Algorithms in Constrained Memory.'' [[ICGA Journal#16_1|ICCA Journal, Vol. 16, No. 1]]
 
* [[Hermann Kaindl]], G. Kainz, A. Leeb, H. Smetana ('''1995'''). ''How to use limited memory in heuristic search''. Proceedings of the Fourteenth International Joint Conference on Artificial Intelligence (IJCAI-95), Montreal, Canada, pp. 236-242.
 
* [[Hermann Kaindl]], G. Kainz, A. Leeb, H. Smetana ('''1995'''). ''How to use limited memory in heuristic search''. Proceedings of the Fourteenth International Joint Conference on Artificial Intelligence (IJCAI-95), Montreal, Canada, pp. 236-242.
 +
* [[Matteo Frigo]] ('''1997'''). ''The weakest reasonable memory model.'' Masters Thesis, [[Massachusetts Institute of Technology]], Department of Electrical Engineering and Computer Science, [http://supertech.csail.mit.edu/papers/frigo-ms-thesis.pdf pdf]
 
* [[Dennis Breuker]] ('''1998'''). ''Memory versus Search in Games''. Ph.D. thesis, [[Maastricht University]], pdf available via [http://www.dennisbreuker.nl/thesis/index.html Dennis Breuker's page]
 
* [[Dennis Breuker]] ('''1998'''). ''Memory versus Search in Games''. Ph.D. thesis, [[Maastricht University]], pdf available via [http://www.dennisbreuker.nl/thesis/index.html Dennis Breuker's page]
 
* [[Harald Prokop]] ('''1999'''). ''Cache-Oblivious Algorithms''. Masters thesis, Department of Electrical Engineering and Computer Science, [[Massachusetts Institute of Technology|MIT]], [http://supertech.csail.mit.edu/papers/Prokop99.pdf pdf] <ref>[https://en.wikipedia.org/wiki/Cache-oblivious_algorithm Cache-oblivious algorithm from Wikipedia]</ref>
 
* [[Harald Prokop]] ('''1999'''). ''Cache-Oblivious Algorithms''. Masters thesis, Department of Electrical Engineering and Computer Science, [[Massachusetts Institute of Technology|MIT]], [http://supertech.csail.mit.edu/papers/Prokop99.pdf pdf] <ref>[https://en.wikipedia.org/wiki/Cache-oblivious_algorithm Cache-oblivious algorithm from Wikipedia]</ref>
 +
* [[Erik D. Demaine]], [[Mathematician#JIMunro|J. Ian Munro]] ('''1999'''). ''[http://erikdemaine.org/papers/Buddy_FSTTCS99/ Fast Allocation and Deallocation with an Improved Buddy System]''. [https://dblp.uni-trier.de/db/conf/fsttcs/fsttcs99.html FSTTCS 1999], [https://en.wikipedia.org/wiki/Lecture_Notes_in_Computer_Science Lecture Notes in Computer Science], Vol. 1738, [https://en.wikipedia.org/wiki/Springer_Science%2BBusiness_Media Springer] <ref>[https://en.wikipedia.org/wiki/Buddy_memory_allocation Buddy memory allocation from Wikipedia]</ref>
 
===2000 ...===  
 
===2000 ...===  
 
* [http://dblp.uni-trier.de/pers/hd/y/Yang:Yue Yue Yang], [http://dblp.uni-trier.de/pers/hd/g/Gopalakrishnan:Ganesh Ganesh Gopalakrishnan], [[Gary Lindstrom]] ('''2002'''). ''Specifying Java Thread Semantics Using a Uniform Memory Model''. [http://dblp.uni-trier.de/db/conf/java/java2002.html#YangGL02 Java Grande 2002], [http://formalverification.cs.utah.edu/yyang/papers/umm_old.pdf pdf]
 
* [http://dblp.uni-trier.de/pers/hd/y/Yang:Yue Yue Yang], [http://dblp.uni-trier.de/pers/hd/g/Gopalakrishnan:Ganesh Ganesh Gopalakrishnan], [[Gary Lindstrom]] ('''2002'''). ''Specifying Java Thread Semantics Using a Uniform Memory Model''. [http://dblp.uni-trier.de/db/conf/java/java2002.html#YangGL02 Java Grande 2002], [http://formalverification.cs.utah.edu/yyang/papers/umm_old.pdf pdf]
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: [http://lwn.net/Articles/254445/ Memory part 4: NUMA support]
 
: [http://lwn.net/Articles/254445/ Memory part 4: NUMA support]
 
: [http://lwn.net/Articles/255364/ Memory part 5: What programmers can do]
 
: [http://lwn.net/Articles/255364/ Memory part 5: What programmers can do]
 +
* [https://genealogy.math.ndsu.nodak.edu/id.php?id=70113 David Gay], [https://dblp.uni-trier.de/pers/hd/e/Ennals:Robert Robert Ennals], [[Eric Brewer]] ('''2007'''). ''[https://dl.acm.org/citation.cfm?id=1296911 Safe manual memory management]''. [https://dblp.uni-trier.de/db/conf/iwmm/ismm2007.html ISMM 2007]
 
* [[David Silver]], [[Richard Sutton]], [[Martin Müller]] ('''2008'''). ''Sample-Based Learning and Search with Permanent and Transient Memories''. In Proceedings of the 25th International Conference on Machine Learning, [http://webdocs.cs.ualberta.ca/%7Esilver/David_Silver/Publications_files/dyna2.pdf pdf]
 
* [[David Silver]], [[Richard Sutton]], [[Martin Müller]] ('''2008'''). ''Sample-Based Learning and Search with Permanent and Transient Memories''. In Proceedings of the 25th International Conference on Machine Learning, [http://webdocs.cs.ualberta.ca/%7Esilver/David_Silver/Publications_files/dyna2.pdf pdf]
 
===2010 ...===
 
===2010 ...===
 
* [[Aaron Becker]], [http://charm.cs.uiuc.edu/people/gengbinzheng Gengbin Zheng], [[Mathematician#LaxKale|Laxmikant Kale]] ('''2011'''). ''Distributed Memory Load Balancing''. [http://www.springer.com/computer/swe/book/978-0-387-09765-7 Encyclopedia of Parallel Computing], [https://en.wikipedia.org/wiki/Springer_Science%2BBusiness_Media Springer]
 
* [[Aaron Becker]], [http://charm.cs.uiuc.edu/people/gengbinzheng Gengbin Zheng], [[Mathematician#LaxKale|Laxmikant Kale]] ('''2011'''). ''Distributed Memory Load Balancing''. [http://www.springer.com/computer/swe/book/978-0-387-09765-7 Encyclopedia of Parallel Computing], [https://en.wikipedia.org/wiki/Springer_Science%2BBusiness_Media Springer]
 
* [https://en.wikipedia.org/wiki/George_Church George Church], [http://www.bme.jhu.edu/people/primary.php?id=1045 Yuan Gao], [http://openwetware.org/wiki/Sriram_Kosuri Sriram Kosuri] ('''2012'''). ''[http://www.sciencemag.org/content/early/2012/08/15/science.1226355 Next-Generation Digital Information Storage in DNA]''. [https://en.wikipedia.org/wiki/Science_%28journal%29 Science] <ref>[http://www.nature.com/news/dna-data-storage-breaks-records-1.11194 DNA data storage breaks records : Nature News & Comment] by [http://www.nature.com/stemcells/about_editor.html Monya Baker], August 16, 2012</ref> <ref>[http://www.talkchess.com/forum/viewtopic.php?t=44826 DNA data storage breaks records] by Terry McCracken, [[CCC]], August 18, 2012</ref>
 
* [https://en.wikipedia.org/wiki/George_Church George Church], [http://www.bme.jhu.edu/people/primary.php?id=1045 Yuan Gao], [http://openwetware.org/wiki/Sriram_Kosuri Sriram Kosuri] ('''2012'''). ''[http://www.sciencemag.org/content/early/2012/08/15/science.1226355 Next-Generation Digital Information Storage in DNA]''. [https://en.wikipedia.org/wiki/Science_%28journal%29 Science] <ref>[http://www.nature.com/news/dna-data-storage-breaks-records-1.11194 DNA data storage breaks records : Nature News & Comment] by [http://www.nature.com/stemcells/about_editor.html Monya Baker], August 16, 2012</ref> <ref>[http://www.talkchess.com/forum/viewtopic.php?t=44826 DNA data storage breaks records] by Terry McCracken, [[CCC]], August 18, 2012</ref>
 +
* [[Matteo Frigo]], [[Charles Leiserson]], [[Harald Prokop]], [https://dblp.uni-trier.de/pers/hd/r/Ramachandran:Sridhar Sridhar Ramachandran] ('''2012'''). ''Cache-Oblivious Algorithms''. [[ACM#TALG|ACM Transactions on Algorithms]], Vol. 8, No. 1, [http://supertech.csail.mit.edu/papers/FrigoLePr12.pdf pdf]
 +
* [https://scholar.google.com/citations?user=1y6pRmEAAAAJ&hl=en Aravinthan Athmanathan], [[Milos Stanisavljevic]], [https://dblp.org/pers/hd/c/Cheon:Junho Junho Cheon], [https://dblp.org/pers/hd/k/Kang:Seokjoon Seokjoon Kang], [https://dblp.org/pers/hd/a/Ahn:Changyong Changyong Ahn], [https://dblp.org/pers/hd/y/Yoon:Junghyuk Junghyuk Yoon], [https://dblp.org/pers/hd/s/Shin:Min=Chul Min-Chul Shin], [https://dblp.org/pers/hd/k/Kim:Taekseung Taekseung Kim], [https://dblp.uni-trier.de/pers/hd/p/Papandreou:Nikolaos Nikolaos Papandreou], [https://scholar.google.co.uk/citations?user=FhioCGgAAAAJ&hl=en Haralampos Pozidis], [https://en.wikipedia.org/wiki/Evangelos_S._Eleftheriou Evangelos Eleftheriou] ('''2014'''). ''[https://www.semanticscholar.org/paper/A-6-bit-drift-resilient-readout-scheme-for-Memory-Athmanathan-Stanisavljevic/072d918e90ffc33c7d07b724a27964ce6062e874 A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory]''. [https://dblp.org/db/conf/asscc/asscc2014.html A-SSCC 2014]
 +
* [[Milos Stanisavljevic]], [https://scholar.google.com/citations?user=1y6pRmEAAAAJ&hl=en Aravinthan Athmanathan], [https://dblp.uni-trier.de/pers/hd/p/Papandreou:Nikolaos Nikolaos Papandreou], [https://scholar.google.co.uk/citations?user=FhioCGgAAAAJ&hl=en Haralampos Pozidis], [https://en.wikipedia.org/wiki/Evangelos_S._Eleftheriou Evangelos Eleftheriou] ('''2015'''). ''[https://www.semanticscholar.org/paper/Phase-change-memory%3A-Feasibility-of-reliable-and-at-Stanisavljevic-Athmanathan/96eef8ca0b005c467031fe66503cbb77e6e9df34 Phase-change memory: Feasibility of reliable multilevel-cell storage and retention at elevated temperatures]''. [https://dblp.org/db/conf/irps/irps2015.html IRPS 2015]
 +
* [https://scholar.google.com/citations?user=1y6pRmEAAAAJ&hl=en Aravinthan Athmanathan], [[Milos Stanisavljevic]], [https://dblp.uni-trier.de/pers/hd/p/Papandreou:Nikolaos Nikolaos Papandreou], [https://scholar.google.co.uk/citations?user=FhioCGgAAAAJ&hl=en Haralampos Pozidis], [https://en.wikipedia.org/wiki/Evangelos_S._Eleftheriou Evangelos Eleftheriou] ('''2016'''). ''[https://ieeexplore.ieee.org/document/7428956 Multilevel-Cell Phase-Change Memory: A Viable Technology]''. [https://dblp.org/db/journals/esticas/esticas6.html IEEE Journal of Emerging and Selected Topics in Circuits and Systems, Vol. 6], No. 1
 
* [[Sylvain Gelly]], [https://ai.google/research/people/KarolKurach Karol Kurach], [http://dblp.uni-trier.de/pers/hd/m/Michalski:Marcin Marcin Michalski], [https://sites.google.com/site/xzhai89/ Xiaohua Zhai] ('''2018'''). ''MemGEN: Memory is All You Need''. [https://arxiv.org/abs/1803.11203 arXiv:1803.11203] <ref>[https://en.wikipedia.org/wiki/April_Fools%27_Day April 01], 2018</ref>
 
* [[Sylvain Gelly]], [https://ai.google/research/people/KarolKurach Karol Kurach], [http://dblp.uni-trier.de/pers/hd/m/Michalski:Marcin Marcin Michalski], [https://sites.google.com/site/xzhai89/ Xiaohua Zhai] ('''2018'''). ''MemGEN: Memory is All You Need''. [https://arxiv.org/abs/1803.11203 arXiv:1803.11203] <ref>[https://en.wikipedia.org/wiki/April_Fools%27_Day April 01], 2018</ref>
 +
* [[Milos Stanisavljevic]], [https://scholar.google.com/citations?user=a7g7yY8AAAAJ&hl=en Thomas Mittelholzer], [https://dblp.uni-trier.de/pers/hd/p/Papandreou:Nikolaos Nikolaos Papandreou], [https://dblp.org/pers/hd/p/Parnell:Thomas_P= Thomas P. Parnell], [https://scholar.google.co.uk/citations?user=FhioCGgAAAAJ&hl=en Haralampos Pozidis] ('''2018'''). ''[https://ieeexplore.ieee.org/document/8351740 Drift-Invariant Detection for Multilevel Phase-Change Memory]''. [https://dblp.org/db/conf/iscas/iscas2018.html#StanisavljevicM18 ISCAS 2018]
  
 
==[[Cognition]]==  
 
==[[Cognition]]==  
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===1980 ...===  
 
===1980 ...===  
 
* [[Marvin Minsky]] ('''1980'''). ''K-Lines: A Theory of Memory''. Cognitive Science 4, 117-133, [http://csjarchive.cogsci.rpi.edu/1980v04/i02/p0117p0133/MAIN.PDF pdf] <ref>[https://en.wikipedia.org/wiki/K-line_%28artificial_intelligence%29 K-line (artificial intelligence) from Wikipedia]</ref>
 
* [[Marvin Minsky]] ('''1980'''). ''K-Lines: A Theory of Memory''. Cognitive Science 4, 117-133, [http://csjarchive.cogsci.rpi.edu/1980v04/i02/p0117p0133/MAIN.PDF pdf] <ref>[https://en.wikipedia.org/wiki/K-line_%28artificial_intelligence%29 K-line (artificial intelligence) from Wikipedia]</ref>
* [[Dennis H. Holding]], [[Robert I. Reynolds]] ('''1982'''). ''[http://link.springer.com/article/10.3758%2FBF03197635?LI=true#page-1 Recall or Evaluation of Chess Positions as Determinants of Chess Skill]''. [http://www.springer.com/psychology/cognitive+psychology/journal/13421 Memory & Cognition], Vol. 10, No. 3, 237-242
+
* [[Dennis H. Holding]], [[Robert I. Reynolds]] ('''1982'''). ''[https://link.springer.com/article/10.3758/BF03197635 Recall or Evaluation of Chess Positions as Determinants of Chess Skill]''. [https://www.springer.com/journal/13421 Memory & Cognition], Vol. 10, No. 3
 
* [[A. Harry Klopf]] ('''1982'''). ''The Hedonistic Neuron: A Theory of Memory, Learning, and Intelligence''. Hemisphere Publishing Corporation, [[University of Michigan]]
 
* [[A. Harry Klopf]] ('''1982'''). ''The Hedonistic Neuron: A Theory of Memory, Learning, and Intelligence''. Hemisphere Publishing Corporation, [[University of Michigan]]
 
===1990 ...===  
 
===1990 ...===  
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==2000 ...==  
 
==2000 ...==  
 
* [https://www.stmintz.com/ccc/index.php?id=293626 Difference in chess between DDR and PC133 SDRAM?] by [[Javier Ros Padilla]], [[CCC]], April 16, 2003
 
* [https://www.stmintz.com/ccc/index.php?id=293626 Difference in chess between DDR and PC133 SDRAM?] by [[Javier Ros Padilla]], [[CCC]], April 16, 2003
* [https://www.stmintz.com/ccc/index.php?id=306858 Another memory latency test] by [[Dieter Bürssner]], [[CCC]], July 17, 2003
+
* [https://www.stmintz.com/ccc/index.php?id=306858 Another memory latency test] by [[Dieter Bürßner]], [[CCC]], July 17, 2003
 
* [http://groups.google.com/group/comp.lang.asm.x86/msg/26c662942c961ecd Re: Static memory allocation] by [[Matt Taylor]], [http://groups.google.com/group/comp.lang.asm.x86/topics comp.lang.asm.x86], July 03, 2004
 
* [http://groups.google.com/group/comp.lang.asm.x86/msg/26c662942c961ecd Re: Static memory allocation] by [[Matt Taylor]], [http://groups.google.com/group/comp.lang.asm.x86/topics comp.lang.asm.x86], July 03, 2004
 
==2005 ...==  
 
==2005 ...==  
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* [http://www.talkchess.com/forum/viewtopic.php?t=38441 MSVC calloc question] by [[Harm Geert Muller]], [[CCC]], March 17, 2011
 
* [http://www.talkchess.com/forum/viewtopic.php?t=38441 MSVC calloc question] by [[Harm Geert Muller]], [[CCC]], March 17, 2011
 
'''2012'''  
 
'''2012'''  
 +
* [http://www.talkchess.com/forum3/viewtopic.php?f=7&t=43770 Memory question] by [[Fermin Serrano]], [[CCC]], May 19, 2012
 
* [http://www.talkchess.com/forum/viewtopic.php?t=44826 DNA data storage breaks records] by Terry McCracken, [[CCC]], August 18, 2012 <ref>[https://en.wikipedia.org/wiki/George_Church George Church], [http://www.bme.jhu.edu/people/primary.php?id=1045 Yuan Gao], [http://openwetware.org/wiki/Sriram_Kosuri Sriram Kosuri] ('''2012'''). ''[http://www.sciencemag.org/content/early/2012/08/15/science.1226355 Next-Generation Digital Information Storage in DNA]''. [https://en.wikipedia.org/wiki/Science_%28journal%29 Science]</ref>
 
* [http://www.talkchess.com/forum/viewtopic.php?t=44826 DNA data storage breaks records] by Terry McCracken, [[CCC]], August 18, 2012 <ref>[https://en.wikipedia.org/wiki/George_Church George Church], [http://www.bme.jhu.edu/people/primary.php?id=1045 Yuan Gao], [http://openwetware.org/wiki/Sriram_Kosuri Sriram Kosuri] ('''2012'''). ''[http://www.sciencemag.org/content/early/2012/08/15/science.1226355 Next-Generation Digital Information Storage in DNA]''. [https://en.wikipedia.org/wiki/Science_%28journal%29 Science]</ref>
 
'''2013'''
 
'''2013'''
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* [http://www.talkchess.com/forum/viewtopic.php?t=61472 What do you do with NUMA?] by [[Matthew Lai]], [[CCC]], September 19, 2016 » [[NUMA]]
 
* [http://www.talkchess.com/forum/viewtopic.php?t=61472 What do you do with NUMA?] by [[Matthew Lai]], [[CCC]], September 19, 2016 » [[NUMA]]
 
* [http://rybkaforum.net/cgi-bin/rybkaforum/topic_show.pl?tid=31867 L3 cache, RAM and other performance factors] by Nimzy, [[Computer Chess Forums|Rybka Forum]], December 04, 2016 » [[Playing Strength]]
 
* [http://rybkaforum.net/cgi-bin/rybkaforum/topic_show.pl?tid=31867 L3 cache, RAM and other performance factors] by Nimzy, [[Computer Chess Forums|Rybka Forum]], December 04, 2016 » [[Playing Strength]]
'''2017'''
+
'''2017 ...'''
 
* [http://www.talkchess.com/forum/viewtopic.php?t=63652 6-men Syzygy from HDD and USB 3.0] by [[Kai Laskos]], [[CCC]], April 04, 2017 » [[Komodo]], [[Playing Strength]], [[Syzygy Bases]], [[Memory#USB3|USB 3.0]]
 
* [http://www.talkchess.com/forum/viewtopic.php?t=63652 6-men Syzygy from HDD and USB 3.0] by [[Kai Laskos]], [[CCC]], April 04, 2017 » [[Komodo]], [[Playing Strength]], [[Syzygy Bases]], [[Memory#USB3|USB 3.0]]
 
* [http://www.talkchess.com/forum/viewtopic.php?t=63886 RAM speed and engine strength] by John Hartmann, [[CCC]], May 03, 2017 » [[Memory#RAM|RAM]], [[Playing Strength]]
 
* [http://www.talkchess.com/forum/viewtopic.php?t=63886 RAM speed and engine strength] by John Hartmann, [[CCC]], May 03, 2017 » [[Memory#RAM|RAM]], [[Playing Strength]]
* [http://www.talkchess.com/forum/viewtopic.php?t=65284 Probing tablebases through USB 3.0] by [[Jon Fredrik Åsvang]], [[CCC]], September 25, 2017 » , [[Syzygy Bases]], [[Memory#USB3|USB 3.0]]
+
* [http://www.talkchess.com/forum/viewtopic.php?t=65284 Probing tablebases through USB 3.0] by [[Jon Fredrik Åsvang]], [[CCC]], September 25, 2017 » [[Syzygy Bases]], [[Memory#USB3|USB 3.0]]
 +
* [http://www.talkchess.com/forum3/viewtopic.php?f=7&t=70586 Prefetch and Threading] by [[Dennis Sceviour]], [[CCC]], April 25, 2019 » [[Thread]], [[Transposition Table]]
 +
==2020 ...==
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* [http://www.talkchess.com/forum3/viewtopic.php?f=7&t=74751 History of Memory Wall in Computer Chess?] by [[Srdja Matovic]], [[CCC]], August 11, 2020
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* [http://www.talkchess.com/forum3/viewtopic.php?f=7&t=75116 Memory management and threads] by [[Chris Whittington]], [[CCC]], September 15, 2020 » [[Thread]]
  
 
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Revision as of 15:29, 28 September 2020

Home * Hardware * Memory

RNA, biological data storage [1]

Memory is the ability to store, retain, and recall information and experiences as researched in cognitive science. Computer memory refers to physical devices used to store data and sequences of instructions (programs) on a temporary or permanent basis, typically distinguished as fast random-access memory and relatively slow data storage.

Flip-Flop

A flip-flop or latch is a one bit memory. For instance a simple relay (K1) with its contact parallel to the On-push-button S2, "remembers" whether last action was pushing S1 (reset) or S2 (set) [2] .

Selbsthaltung.gif

A RS flip-flop is a pair of cross-coupled NAND or NOR-gates, where the outputs are feed back to the inputs. A D flip-flop, the most common flip-flop, stores the input D with the rising edge (0-1 transition) of a clock.

RS flip-flop D flip-flop Discrete
RS flipflop.svg
D-Type Flip-flop.svg
Flipflop6as.jpg
R-S mk2.gif
Edge triggered D flip flop.svg
from two NOR (red == 1) [3] from six NAND [4] PDP-6 flip-flop [5] [6]

N-Bit Latches

N-Bit latches are arrays of one-bit latches or flip-flops typically as wide as a connected parallel data-bus. They may be used as a registers or scratchpad RAM inside a central processing unit.

RAM

Random access memory is a fast form of computer memory and refers to the idea that any piece of data can be stored and retrieved in a constant time, regardless of its physical location and whether or not it is related to the previous piece of data.

Static RAM

Static RAM (SRAM) is an array of latches, where each latch has a unique address, which connects the addressed latch to its data-bus, often used as CPU cache.

Dynamic RAM

Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an electronic circuit. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically, which is the reason to call that memory dynamic. Since DRAM takes only one transistor and capacitor per bit, it is therefor used as cheap main memory part of recent computer data storage, despite its worse latency compared to SRAM.

Square array of mosfet cells read.png

DRAM write at a 4 by 4 array [7]

ROM

Read-only memory (ROM) is a class of storage programmed once and mainly used to distribute firmware. EPROMs have a small quartz window which admits UV light for erasure [8] . ROM or EPROM were often embedded inside a microcontroller in conjunction with some RAM. They were often used in dedicated chess computers.

EPROMs National Semiconductor.jpg

National Semiconductor EPROMs 2764 and 2716 [9]

Since each data-bit stored in a ROM is a boolean function of its inputs or address, a ROM is also used to implement combinatorial logic.

Persistence

Auxiliary Storage

Beside the computer's random access main memory, auxiliary storage refer to mass storage like optical discs, and magnetic storage hard disk drives. Those devices are usually connected via a serial bus, and accessed via streams.

Intelligent Chess 1 20x20.JPG

Compact Cassette as Auxiliary Storage in Intelligent Chess [10]

USB 3.0

Historical Data Storage

Coincident-current magnetic core.svg
Plated wire memory from Wikipedia
Pamiec bebnowa 1.jpg

Memory Hierarchy

ComputerMemoryHierarchy.svg

Memory Management

Todays processors utilize all the above types of memory from small and fast to large but slow within the concepts of virtual memory, paging, protection and various caches.

Virtual Memory

Page table actions.svg
Virtual address space and physical address space relationship.svg
Physical address translation [12] Virtual and physical address space [13]

Paging

Page table
Page replacement algorithm
Paging
Demand Paging
Page fault
Copy-on-write

TLB

Huge Pages

Note that what Windows calls "large pages," Linux and Unix call "huge pages" or "huge TLB pages (x86 and x86-64)

Memory Model

Shared Memory

Shared Memory:

False sharing from Wikipedia

Cache

Cache:

MSI protocol from Wikipedia
MESI protocol from Wikipedia
MOESI protocol from Wikipedia
assembly - The prefetch instruction - Stack Overflow
Data Prefetch Support - GNU Project - Free Software Foundation (FSF)
Software prefetching considered harmful by Linus Torvalds, LWN.net, May 19, 2011

Segmentation

Allocation

Manual memory management
Memory leak
Garbage collection

Memory Footprint

Beside their individual memory footprint, chess programs have to deal with huge memory areas of transposition table and possibly caches for endgame table- or bitbases and their relative huge random access latencies.

Miles Davis, Wayne Shorter, Herbie Hancock, Ron Carter, Tony Williams
Monika Malczak, Mateusz Gramburg, Paweł Zwierzyński-Pióro, Michał Szeligowski

Multiprocessing

Memory versus Search

See also

Publications

Computer Memory

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Memory part 1
Memory part 2: CPU caches
Memory part 3: Virtual Memory
Memory part 4: NUMA support
Memory part 5: What programmers can do

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Cognition

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  • Adriaan de Groot (1966). Perception and Memory versus Thought: Some Old Ideas and Recent Findings. Problem Solving: Research, Method, and Theory (ed. B. Kleinmuntz), pp. 19-50. John Wiley, New York.

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Forum Posts

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External Links

Computer Memory

Gustavo Duarte's Blog

from Best Of by Gustavo Duarte:

Cognition

Neuroscience

Misc

References

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