Difference between revisions of "Memory"

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[https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory] (DRAM) is a type of random access memory that stores each bit of data in a separate [https://en.wikipedia.org/wiki/Capacitor capacitor] within an electronic circuit. Since capacitors leak charge, the information eventually fades unless the capacitor charge is [https://en.wikipedia.org/wiki/Memory_refresh refreshed] periodically, which is the reason to call that memory dynamic. Since DRAM takes only one [https://en.wikipedia.org/wiki/Transistor transistor] and capacitor per bit, it is therefor used as cheap main memory part of recent [https://en.wikipedia.org/wiki/Computer_data_storage computer data storage], despite its worse latency compared to SRAM.
 
[https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory] (DRAM) is a type of random access memory that stores each bit of data in a separate [https://en.wikipedia.org/wiki/Capacitor capacitor] within an electronic circuit. Since capacitors leak charge, the information eventually fades unless the capacitor charge is [https://en.wikipedia.org/wiki/Memory_refresh refreshed] periodically, which is the reason to call that memory dynamic. Since DRAM takes only one [https://en.wikipedia.org/wiki/Transistor transistor] and capacitor per bit, it is therefor used as cheap main memory part of recent [https://en.wikipedia.org/wiki/Computer_data_storage computer data storage], despite its worse latency compared to SRAM.
 
* [https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory from Wikipedia]
 
* [https://en.wikipedia.org/wiki/Dynamic_random_access_memory Dynamic random access memory from Wikipedia]
: [https://en.wikipedia.org/wiki/SDRAM Synchronous dynamic random access memory (SDRAM)]
+
* [https://en.wikipedia.org/wiki/SDRAM Synchronous dynamic random access memory (SDRAM)]
: [https://en.wikipedia.org/wiki/DDR_SDRAM DDR SDRAM] with [https://en.wikipedia.org/wiki/Double_data_rate Double data rate]
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* [https://en.wikipedia.org/wiki/DDR_SDRAM DDR SDRAM] with [https://en.wikipedia.org/wiki/Double_data_rate Double data rate]
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** <span id="DDR2"></span>[https://en.wikipedia.org/wiki/DDR2_SDRAM DDR2 SDRAM]
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** <span id="DDR3"></span>[https://en.wikipedia.org/wiki/DDR3_SDRAM DDR3 SDRAM]
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** <span id="DDR4"></span>[https://en.wikipedia.org/wiki/DDR4_SDRAM DDR4 SDRAM]
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** <span id="DDR5"></span>[https://en.wikipedia.org/wiki/DDR5_SDRAM DDR5 SDRAM]
 
* [https://en.wikipedia.org/wiki/Interleaved_memory Interleaved memory]
 
* [https://en.wikipedia.org/wiki/Interleaved_memory Interleaved memory]
 
* [https://en.wikipedia.org/wiki/SDRAM_latency SDRAM latency]
 
* [https://en.wikipedia.org/wiki/SDRAM_latency SDRAM latency]
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Since each data-bit stored in a ROM is a boolean function of its inputs or address, a ROM is also used to implement [[Combinatorial Logic|combinatorial logic]].
 
Since each data-bit stored in a ROM is a boolean function of its inputs or address, a ROM is also used to implement [[Combinatorial Logic|combinatorial logic]].
 
* [https://en.wikipedia.org/wiki/Read-only_memory Read-only memory from Wikipedia]
 
* [https://en.wikipedia.org/wiki/Read-only_memory Read-only memory from Wikipedia]
* [https://en.wikipedia.org/wiki/Non-volatile_memory Non-volatile memory from Wikipedia]
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=Persistence=
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* [https://en.wikipedia.org/wiki/Persistence_(computer_science) Persistence]
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* [https://en.wikipedia.org/wiki/Non-volatile_memory Non-volatile memory]
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* [https://en.wikipedia.org/wiki/Non-volatile_random-access_memory Non-volatile random-access memory]
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* [https://en.wikipedia.org/wiki/Persistent_memory Persistent memory]
  
 
=Auxiliary Storage=  
 
=Auxiliary Storage=  
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: [http://lwn.net/Articles/254445/ Memory part 4: NUMA support]
 
: [http://lwn.net/Articles/254445/ Memory part 4: NUMA support]
 
: [http://lwn.net/Articles/255364/ Memory part 5: What programmers can do]
 
: [http://lwn.net/Articles/255364/ Memory part 5: What programmers can do]
 +
* [https://genealogy.math.ndsu.nodak.edu/id.php?id=70113 David Gay], [https://dblp.uni-trier.de/pers/hd/e/Ennals:Robert Robert Ennals], [[Eric Brewer]] ('''2007'''). ''[https://dl.acm.org/citation.cfm?id=1296911 Safe manual memory management]''. [https://dblp.uni-trier.de/db/conf/iwmm/ismm2007.html ISMM 2007]
 
* [[David Silver]], [[Richard Sutton]], [[Martin Müller]] ('''2008'''). ''Sample-Based Learning and Search with Permanent and Transient Memories''. In Proceedings of the 25th International Conference on Machine Learning, [http://webdocs.cs.ualberta.ca/%7Esilver/David_Silver/Publications_files/dyna2.pdf pdf]
 
* [[David Silver]], [[Richard Sutton]], [[Martin Müller]] ('''2008'''). ''Sample-Based Learning and Search with Permanent and Transient Memories''. In Proceedings of the 25th International Conference on Machine Learning, [http://webdocs.cs.ualberta.ca/%7Esilver/David_Silver/Publications_files/dyna2.pdf pdf]
 
===2010 ...===
 
===2010 ...===
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* [http://www.talkchess.com/forum/viewtopic.php?t=38441 MSVC calloc question] by [[Harm Geert Muller]], [[CCC]], March 17, 2011
 
* [http://www.talkchess.com/forum/viewtopic.php?t=38441 MSVC calloc question] by [[Harm Geert Muller]], [[CCC]], March 17, 2011
 
'''2012'''  
 
'''2012'''  
 +
* [http://www.talkchess.com/forum3/viewtopic.php?f=7&t=43770 Memory question] by [[Fermin Serrano]], [[CCC]], May 19, 2012
 
* [http://www.talkchess.com/forum/viewtopic.php?t=44826 DNA data storage breaks records] by Terry McCracken, [[CCC]], August 18, 2012 <ref>[https://en.wikipedia.org/wiki/George_Church George Church], [http://www.bme.jhu.edu/people/primary.php?id=1045 Yuan Gao], [http://openwetware.org/wiki/Sriram_Kosuri Sriram Kosuri] ('''2012'''). ''[http://www.sciencemag.org/content/early/2012/08/15/science.1226355 Next-Generation Digital Information Storage in DNA]''. [https://en.wikipedia.org/wiki/Science_%28journal%29 Science]</ref>
 
* [http://www.talkchess.com/forum/viewtopic.php?t=44826 DNA data storage breaks records] by Terry McCracken, [[CCC]], August 18, 2012 <ref>[https://en.wikipedia.org/wiki/George_Church George Church], [http://www.bme.jhu.edu/people/primary.php?id=1045 Yuan Gao], [http://openwetware.org/wiki/Sriram_Kosuri Sriram Kosuri] ('''2012'''). ''[http://www.sciencemag.org/content/early/2012/08/15/science.1226355 Next-Generation Digital Information Storage in DNA]''. [https://en.wikipedia.org/wiki/Science_%28journal%29 Science]</ref>
 
'''2013'''
 
'''2013'''

Latest revision as of 21:16, 4 April 2020

Home * Hardware * Memory

RNA, biological data storage [1]

Memory is the ability to store, retain, and recall information and experiences as researched in cognitive science. Computer memory refers to physical devices used to store data and sequences of instructions (programs) on a temporary or permanent basis, typically distinguished as fast random-access memory and relatively slow data storage.

Flip-Flop

A flip-flop or latch is a one bit memory. For instance a simple relay (K1) with its contact parallel to the On-push-button S2, "remembers" whether last action was pushing S1 (reset) or S2 (set) [2] .

Selbsthaltung.gif

A RS flip-flop is a pair of cross-coupled NAND or NOR-gates, where the outputs are feed back to the inputs. A D flip-flop, the most common flip-flop, stores the input D with the rising edge (0-1 transition) of a clock.

RS flip-flop D flip-flop Discrete
RS flipflop.svg
D-Type Flip-flop.svg
Flipflop6as.jpg
R-S mk2.gif
Edge triggered D flip flop.svg
from two NOR (red == 1) [3] from six NAND [4] PDP-6 flip-flop [5] [6]

N-Bit Latches

N-Bit latches are arrays of one-bit latches or flip-flops typically as wide as a connected parallel data-bus. They may be used as a registers or scratchpad RAM inside a central processing unit.

RAM

Random access memory is a fast form of computer memory and refers to the idea that any piece of data can be stored and retrieved in a constant time, regardless of its physical location and whether or not it is related to the previous piece of data.

Static RAM

Static RAM (SRAM) is an array of latches, where each latch has a unique address, which connects the addressed latch to its data-bus, often used as CPU cache.

Dynamic RAM

Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an electronic circuit. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically, which is the reason to call that memory dynamic. Since DRAM takes only one transistor and capacitor per bit, it is therefor used as cheap main memory part of recent computer data storage, despite its worse latency compared to SRAM.

Square array of mosfet cells read.png

DRAM write at a 4 by 4 array [7]

ROM

Read-only memory (ROM) is a class of storage programmed once and mainly used to distribute firmware. EPROMs have a small quartz window which admits UV light for erasure [8] . ROM or EPROM were often embedded inside a microcontroller in conjunction with some RAM. They were often used in dedicated chess computers.

EPROMs National Semiconductor.jpg

National Semiconductor EPROMs 2764 and 2716 [9]

Since each data-bit stored in a ROM is a boolean function of its inputs or address, a ROM is also used to implement combinatorial logic.

Persistence

Auxiliary Storage

Beside the computer's random access main memory, auxiliary storage refer to mass storage like optical discs, and magnetic storage hard disk drives. Those devices are usually connected via a serial bus, and accessed via streams.

Intelligent Chess 1 20x20.JPG

Compact Cassette as Auxiliary Storage in Intelligent Chess [10]

USB 3.0

Historical Data Storage

Coincident-current magnetic core.svg
Plated wire memory from Wikipedia
Pamiec bebnowa 1.jpg

Memory Hierarchy

ComputerMemoryHierarchy.svg

Memory Management

Todays processors utilize all the above types of memory from small and fast to large but slow within the concepts of virtual memory, paging, protection and various caches.

Virtual Memory

Page table actions.svg
Virtual address space and physical address space relationship.svg
Physical address translation [12] Virtual and physical address space [13]

Paging

Page table
Page replacement algorithm
Paging
Demand Paging
Page fault
Copy-on-write

TLB

Huge Pages

Note that what Windows calls "large pages," Linux and Unix call "huge pages" or "huge TLB pages (x86 and x86-64)

Memory Model

Shared Memory

Shared Memory:

False sharing from Wikipedia

Cache

Cache:

MSI protocol from Wikipedia
MESI protocol from Wikipedia
MOESI protocol from Wikipedia
assembly - The prefetch instruction - Stack Overflow
Data Prefetch Support - GNU Project - Free Software Foundation (FSF)
Software prefetching considered harmful by Linus Torvalds, LWN.net, May 19, 2011

Segmentation

Allocation

Manual memory management
Memory leak
Garbage collection

Memory Footprint

Beside their individual memory footprint, chess programs have to deal with huge memory areas of transposition table and possibly caches for endgame table- or bitbases and their relative huge random access latencies.

Miles Davis, Wayne Shorter, Herbie Hancock, Ron Carter, Tony Williams
Monika Malczak, Mateusz Gramburg, Paweł Zwierzyński-Pióro, Michał Szeligowski

Multiprocessing

Memory versus Search

See also

Publications

Computer Memory

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Memory part 1
Memory part 2: CPU caches
Memory part 3: Virtual Memory
Memory part 4: NUMA support
Memory part 5: What programmers can do

2010 ...

Cognition

1960 ...

  • Adriaan de Groot (1966). Perception and Memory versus Thought: Some Old Ideas and Recent Findings. Problem Solving: Research, Method, and Theory (ed. B. Kleinmuntz), pp. 19-50. John Wiley, New York.

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Forum Posts

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2011

2012

2013

2014

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External Links

Computer Memory

Gustavo Duarte's Blog

from Best Of by Gustavo Duarte:

Cognition

Neuroscience

Misc

References

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