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a chess program by [[Marc Boulé]], written in [[C]]. It was primarily used as test-bed for hardware based [[FPGA]] [[Move Generation|move generation]], which was subject of Boulé's Masters thesis in 2002 <ref>[[Marc Boulé]] ('''2002'''). ''An FPGA Move Generator for the Game of Chess''. Masters thesis, [[McGill University]], (Supervisor: [[Zeljko Zilic]], Co-Supervisor: [[Monroe Newborn|Monty Newborn]]), [http://www.iml.ece.mcgill.ca/%7Emboule/files/mbthesis02.pdf pdf]</ref>. The FPGA approach performs a [[Belle#Hardware|Belle]] like move generation method with find '''victim''' and find '''aggressor''' cycles in [[MVV-LVA]] manner. The move generator includes a [https://en.wikipedia.org/wiki/Conventional_PCI PCI] interface to connect it to the PC running MBChess. Communication is done via different commands, such as to instruct the move generator to [[Unmake Move|undo]] the currently stored move, generate and return the next move and [[Make Move|execute]] that move on its internal FPGA [[Board Representation|board representation]]. In total, 10,804 out of 18,816 [[FPGA#LC|logic cells]] of a [https://en.wikipedia.org/wiki/Xilinx Xilinx] XCV800 <ref>[https://www.stmintz.com/ccc/index.php?id=292813 Re: Attention - Slater Wold] by [[Marc Boulé]], [[CCC]], April 10, 2003</ref> were used, 10,104 as [https://en.wikipedia.org/wiki/Lookup_table#Hardware_LUTs LUT], 700 as RAM <ref>[https://www.stmintz.com/ccc/index.php?id=251005 Re: Thesis by Marc Boule] by [[Marc Boulé]], [[CCC]], September 08, 2002</ref>.

A block diagram of a chess square with transmitter (TX) and the receiver (RX) <ref>[[Marc Boulé]] ('''2002'''). ''An FPGA Move Generator for the Game of Chess''. Masters thesis, [[McGill University]], (Supervisor: [[Zeljko Zilic]], Co-Supervisor: [[Monroe Newborn|Monty Newborn]]), [http://www.iml.ece.mcgill.ca/%7Emboule/files/mbthesis02.pdf pdf]</ref>

MBChess is a very basic chess program, without [[Opening Book|opening book]], only rudimentary [[Evaluation|evaluation]], i.e. almost no [[King Safety|king safety]], and without [[Null Move Pruning |null move pruning]]. The reported ratings obtained on [[FICS]] are 1844 and 1692 for MBChess+FPGA and MBChess respectively <ref>[[Marc Boulé]], [[Zeljko Zilic]] ('''2002'''). ''An FPGA Move Generator for the Game of Chess''. [[ICGA Journal]]#25_2|ICGA Journal, Vol. 25, No. 2, pp. 8, [http://iml.ece.mcgill.ca/~mboule/files/icga02.pdf pdf]]</ref>. Marc Boulé further concluded a bit disappointing results <ref>[https://www.stmintz.com/ccc/index.php?id=221124 A Response From Marc Boule] by [[Slater Wold]], [[CCC]], April 02, 2002</ref>. Even though the pure move generation speed is almost 5 times faster, when using full heuristics, this drops to about 2 times faster. He found that his FPGA move generator, can at best, make/unmake 10M moves a second, which due to PCI bus saturation, will not even transfer from FPGA to PC. [[Crafty]] could already make/unmake 30M moves a second on that machine, which implies the only way to speedup Crafty would be to make an FPGA with search and evaluation.

* [[Marc Boulé]] ('''2002'''). ''An FPGA Move Generator for the Game of Chess''. Masters thesis, [[McGill University]], (Supervisor: [[Zeljko Zilic]], Co-Supervisor: [[Monroe Newborn|Monty Newborn]]), [http://www.iml.ece.mcgill.ca/%7Emboule/files/mbthesis02.pdf pdf]* [[Marc Boulé]], [[Zeljko Zilic]] ('''2002'''). ''An FPGA Move Generator for the Game of Chess''. [[McGill University]],[http://www.iml.ece.mcgill.ca/%7Emboule/files/cicc02.pdf pdf]* [[Marc Boulé]], [[Zeljko Zilic]] ('''2002'''). ''An FPGA Move Generator for the Game of Chess''. [[ICGA Journal]]#25_2|ICGA Journal, Vol. 25, No. 2, [http://iml.ece.mcgill.ca/~mboule/files/icga02.pdf pdf]]