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System architecture of Hydra <ref>[https://de.wikipedia.org/wiki/Hydra_(Schachcomputer) Hydra (Schachcomputer) – Wikipedia.de] (German)</ref>ran on a [https://en.wikipedia.org/wiki/Myrinet Myrinet] interconnected [[Linux]] [https://en.wikipedia.org/wiki/Computer_cluster cluster] of four (later eight) dual [[IBM PC|PC]] server nodes able to handle two [https://en.wikipedia.org/wiki/Conventional_PCI PCI] buses, which are conneced to a FPGA card each, simultaneously. The [[Parallel Search|distributed search]] algorithm ran on the [[x86]] nodes as [https://en.wikipedia.org/wiki/Message_Passing_Interface MPI] [[Process|processes]], where the last three [[Ply|plies]] of an n-ply search including [[Quiescence Search|quiescence]] and all [[Evaluation|evaluations]] are delegated to the FPGA card, typically 100.000 times per second and processor. For further information see the [[Brutus#Description|description]] of [[Brutus]].