Difference between revisions of "H8"
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=Architecture= | =Architecture= | ||
The basic architecture of the H8 was influenced by the [[Digital Equipment Corporation|DEC]] [[PDP-11]], with sixteen 8-bit registers (R0H, R0L, ..., R7H, R7L), with some instructons also accessible as eight 16-bit registers (R0 - R7), where R7 is the [https://en.wikipedia.org/wiki/Call_stack#STACK-POINTER stack pointer], 16-bit [https://en.wikipedia.org/wiki/Program_counter program counter], 8-bit condition code register (CCR) and a variety of addressing modes. Opposed to the PDP-11, H8 is a [[Big-endian|big-endian]] machine, since the upper 8 bits of a 16-bit word are stored at the even word address, the lower 8 bits at the odd address. The H8/300 has a [https://en.wiktionary.org/wiki/concise concise] set of 57 [https://en.wikipedia.org/wiki/Reduced_instruction_set_computing RISC]-like instructions, 2 or 4 bytes long <ref>[https://www.classes.cs.uchicago.edu/archive/2006/winter/23000-1/docs/h8300.pdf H8/300 Programming Manual] (pdf)</ref>. Arithmetic, logic, shift and bit manipulation instructions are performed as register-to-register operations, or with immediate data. | The basic architecture of the H8 was influenced by the [[Digital Equipment Corporation|DEC]] [[PDP-11]], with sixteen 8-bit registers (R0H, R0L, ..., R7H, R7L), with some instructons also accessible as eight 16-bit registers (R0 - R7), where R7 is the [https://en.wikipedia.org/wiki/Call_stack#STACK-POINTER stack pointer], 16-bit [https://en.wikipedia.org/wiki/Program_counter program counter], 8-bit condition code register (CCR) and a variety of addressing modes. Opposed to the PDP-11, H8 is a [[Big-endian|big-endian]] machine, since the upper 8 bits of a 16-bit word are stored at the even word address, the lower 8 bits at the odd address. The H8/300 has a [https://en.wiktionary.org/wiki/concise concise] set of 57 [https://en.wikipedia.org/wiki/Reduced_instruction_set_computing RISC]-like instructions, 2 or 4 bytes long <ref>[https://www.classes.cs.uchicago.edu/archive/2006/winter/23000-1/docs/h8300.pdf H8/300 Programming Manual] (pdf)</ref>. Arithmetic, logic, shift and bit manipulation instructions are performed as register-to-register operations, or with immediate data. | ||
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| + | =H8 Chess Programs= | ||
| + | * [[:Category:H8]] | ||
=Manuals= | =Manuals= | ||
Revision as of 14:01, 18 May 2020
.JPG)
H8,
a family of 8-bit microcontrollers, since the early 1990s developed and made by Hitachi, in April 2003 transferred to Renesas Technology. The chip consists of a CPU, various read only and random access memory variations, including parallel and serial I/O-ports, AD-converter, and timer. The controller was used in several dedicated chess computers of the early 90s.
Architecture
The basic architecture of the H8 was influenced by the DEC PDP-11, with sixteen 8-bit registers (R0H, R0L, ..., R7H, R7L), with some instructons also accessible as eight 16-bit registers (R0 - R7), where R7 is the stack pointer, 16-bit program counter, 8-bit condition code register (CCR) and a variety of addressing modes. Opposed to the PDP-11, H8 is a big-endian machine, since the upper 8 bits of a 16-bit word are stored at the even word address, the lower 8 bits at the odd address. The H8/300 has a concise set of 57 RISC-like instructions, 2 or 4 bytes long [2]. Arithmetic, logic, shift and bit manipulation instructions are performed as register-to-register operations, or with immediate data.
H8 Chess Programs
Manuals
- Hitachi Single-Chip Microcomputer H8/3297 Series Hardware Manual (pdf)
- H8/300 Programming Manual (pdf)
External Links
- H8 Family | Renesas Electronics
- H8 Family from Wikipedia
- H8/330 from Schachcomputer.info Wiki (German)
- H8/300 Application Binary Interface for GCC - GNU Project, Free Software Foundation (FSF)
References
- ↑ Image by ZyMOS, February 28, 2009, H8 Family from Wikipedia
- ↑ H8/300 Programming Manual (pdf)
