GPU (Graphics Processing Unit),
a specialized processor primarily intended to fast image processing. GPUs may have more raw computing power than general purpose CPUs but need a specialized and parallelized way of programming. Leela Chess Zero has proven that a Best-first Monte-Carlo Tree Search (MCTS) with deep learning methodology will work with GPU architectures.
- 1 History
- 2 GPU in Computer Chess
- 3 GPU Chess Engines
- 4 GPGPU
- 5 Hardware Model
- 6 Programming Model
- 7 Memory Model
- 8 Instruction Throughput
- 9 Host-Device Latencies
- 10 Deep Learning
- 11 Architectures
- 11.1 AMD
- 11.2 Apple
- 11.3 ARM
- 11.4 Intel
- 11.5 Nvidia
- 11.6 Qualcomm
- 11.7 PowerVR
- 11.8 Vivante Corporation
- 12 See also
- 13 Publications
- 14 Forum Posts
- 15 External Links
- 16 References
In the 1970s and 1980s RAM was expensive and Home Computers used custom graphics chips to operate directly on registers/memory without a dedicated frame buffer, like TIAin the Atari VCS gaming system, GTIA+ANTIC in the Atari 400/800 series, or Denise+Agnus in the Commodore Amiga series. The 1990s would make 3D graphics and 3D modeling more popular, especially for video games. Cards specifically designed to accelerate 3D math, such as the 3dfx Voodoo2, were used by the video game community to play 3D graphics. Some game engines could use instead the SIMD-capabilities of CPUs such as the Intel MMX instruction set or AMD's 3DNow! for real-time rendering. Sony's 3D capable chip used in the PlayStation (1994) and Nvidia's 2D/3D combi chips like NV1 (1995) coined the term GPU for 3D graphics hardware acceleration. With the advent of the unified shader architecture, like in Nvidia Tesla (2006), ATI/AMD TeraScale (2007) or Intel GMA X3000 (2006), GPGPU frameworks like CUDA and OpenCL emerged and gained in popularity.
GPU in Computer Chess
There are in main three approaches how to use a GPU for Chess:
- As an accelerator in Lc0: run a neural network for position evaluation on GPU.
- Offload the search in Zeta: run a parallel game tree search with move generation and position evaluation on GPU.
- As an hybrid in perft_gpu: expand the game tree to a certain degree on CPU and offload to GPU to compute the sub-tree.
GPU Chess Engines
Early efforts to leverage a GPU for general-purpose computing required reformulating computational problems in terms of graphics primitives via graphics APIs like OpenGL or DirextX, followed by first GPGPU frameworks such as Sh/RapidMind or Brook and finally CUDA and OpenCL.
- AMD OpenCL Developer Community
- ROCm Homepage
- AMD OpenCL Programming Guide
- AMD OpenCL Optimization Guide
- RDNA Instruction Set
- Vega Instruction Set
Since macOS 10.14 Mojave a transition from OpenCL to Metal is recommended by Apple.
- Apple OpenCL Developer
- Apple Metal Developer
- Apple Metal Programming Guide
- Metal Shading Language Specification
- oneAPI (Intel)
- C++ AMP (Microsoft)
- DirectCompute (Microsoft)
- OpenACC (offload directives)
- OpenMP (offload directives)
A common scheme on GPUs is to run multiple threads in SIMT fashion and a multitude of SIMT waves on the same SIMD unit to hide memory latencies. Multiple processing elements (GPU cores) are members of a SIMD unit, multiple SIMD units are coupled to a compute unit, with up to hundreds of compute units present on a discrete GPU. The actual SIMD units may have architecture dependent different numbers of cores (SIMD8, SIMD16, SIMD32), and different computation abilities, floating-point and/or integer with specific bit-width of the FPU/ALU and registers. There is a difference between a vector-processor with variable bit-width and SIMD units with fix bit-width cores. Different architecture white papers from different vendors leave room for speculation about the concrete underlying hardware implementation and the concrete classification as hardware architecture. Scalar units present in the compute unit perform special functions the SIMD units are not capable of and MMAC units (matrix-multiply-accumulate units) are used to speed up neural networks further.
A parallel programming model for GPGPU can be data-parallel, task-parallel, a mixture of both, or with libraries and offload-directives also implicitly-parallel. Single GPU threads (work-items in OpenCL) are coupled to a block (work-group in OpenCL) and one or multiple blocks form the grid (NDRange in OpenCL) to be executed on the GPU device. The members of a block resp. work-group can be usually synchronized and have access to the same scratch-pad memory, with an architecture limit of how many threads a block can hold and how many threads can run in total concurrently on the device.
OpenCL offers the following memory model for the programmer:
- __private - usually registers, accessable only by a single work-item resp. thread.
- __local - scratch-pad memory shared across work-items of a work-group resp. threads of block.
- __constant - read-only memory.
- __global - usually VRAM, accessable by all work-items resp. threads.
- 128 KiB private memory per compute unit
- 48 KiB (16 KiB) local memory per compute unit (configurable)
- 64 KiB constant memory
- 8 KiB constant cache per compute unit
- 16 KiB (48 KiB) L1 cache per compute unit (configurable)
- 768 KiB L2 cache
- 1.5 GiB to 3 GiB global memory
- 256 KiB private memory per compute unit
- 64 KiB local memory per compute unit
- 64 KiB constant memory
- 16 KiB constant cache per four compute units
- 16 KiB L1 cache per compute unit
- 768 KiB L2 cache
- 3 GiB to 6 GiB global memory
GPUs are used in HPC environments because of their good FLOP/Watt ratio. The instruction throughput in general depends on the architecture (like Nvidia's Tesla, Fermi, Kepler, Maxwell or AMD's TeraScale, GCN, RDNA), the brand (like Nvidia GeForce, Quadro, Tesla or AMD Radeon, Radeon Pro, Radeon Instinct) and the specific model.
Integer Instruction Throughput
- The 32-bit integer performance can be architecture and operation depended less than 32-bit FLOP or 24-bit integer performance.
- In general GPU registers and Vector-ALUs are 32-bit wide and have to emulate 64-bit integer operations.
- Some architectures offer higher throughput with lower precision. They quadruple the INT8 or octuple the INT4 throughput.
Floating-Point Instruction Throughput
- Consumer GPU performance is measured usually in single-precision (32-bit) floating-point FMA (fused-multiply-add) throughput.
- Consumer GPUs have in general a lower ratio (FP32:FP64) for double-precision (64-bit) floating-point operations throughput than server brand GPUs.
- Some GPGPU architectures offer half-precision (16-bit) floating-point operation throughput with an FP32:FP16 ratio of 1:2.
- With Nvidia Volta series TensorCores were introduced. They offer FP16xFP16+FP32, matrix-multiplication-accumulate-units, used to accelerate neural networks. Turing's 2nd gen TensorCores add FP16, INT8, INT4 optimized computation. Amperes's 3rd gen adds support for BF16, TF32, FP64 and sparsity acceleration.
AMD Matrix Cores
- AMD released 2020 its server-class CDNA architecture with Matrix Cores which support MFMA (matrix-fused-multiply-add) operations on various data types like INT8, FP16, BF16, FP32.
Intel XMX Cores
- Intel plans XMX, Xe Matrix eXtensions, for its upcoming Xe discrete GPU series.
Nvidia GeForce GTX 580 (Fermi, CC 2.0) - 32-bit integer operations/clock cycle per compute unit 
MAD 16 MUL 16 ADD 32 Bit-shift 16 Bitwise XOR 32
Max theoretic ADD operation throughput: 32 Ops x 16 CUs x 1544 MHz = 790.528 GigaOps/sec
AMD Radeon HD 7970 (GCN 1.0) - 32-bit integer operations/clock cycle per processing element 
MAD 1/4 MUL 1/4 ADD 1 Bit-shift 1 Bitwise XOR 1
Max theoretic ADD operation throughput: 1 Op x 2048 PEs x 925 MHz = 1894.4 GigaOps/sec
One reason GPUs are not used as accelerators for chess engines is the host-device latency, aka. kernel-launch-overhead. Nvidia and AMD have not published official numbers, but in practice there is a measurable latency for null-kernels of 5 microseconds  up to 100s of microseconds . One solution to overcome this limitation is to couple tasks to batches to be executed in one run .
GPUs are much more suited than CPUs to implement and train Convolutional Neural Networks (CNN), and were therefore also responsible for the deep learning boom, also affecting game playing programs combining CNN with MCTS, as pioneered by Google DeepMind's AlphaGo and AlphaZero entities in Go, Shogi and Chess using TPUs, and the open source projects Leela Zero headed by Gian-Carlo Pascutto for Go and its Leela Chess Zero adaption.
The market is split into two categories, integrated and discrete GPUs. The first being the most important by quantity, the second by performance. Discrete GPUs are divided as consumer brands for playing 3D games, professional brands for CAD/CGI programs and server brands for big-data and number-crunching workloads. Each brand offering different feature sets in driver, VRAM, or computation abilities.
AMD line of discrete GPUs is branded as Radeon for consumer, Radeon Pro for professional and Radeon Instinct for server.
CDNA architecture in MI100 HPC-GPU with Matrix Cores was unveiled in November, 2020.
RDNA 2.0 cards were unveiled on October 28, 2020.
RDNA 1.0 cards were unveiled on July 7, 2019.
Vega GCN 5th gen
Vega cards were unveiled on August 14, 2017.
Polaris GCN 4th gen
Polaris cards were first released in 2016.
Apple released its M1 SoC (system on a chip) with integrated GPU for desktops and notebooks in 2020.
The ARM Mali GPU variants can be found on various systems on chips (SoCs) from different vendors. Since Midgard (2012) with unified-shader-model OpenCL support is offered.
Intel Xe line of GPUs (released since 2020) is divided as Xe-LP (low-power), Xe-HPG (high-performance-gaming), Xe-HP (high-performace) and Xe-HPC (high-performance-computing).
Nvidia line of discrete GPUs is branded as GeForce for consumer, Quadro for professional and Tesla for server.
The Ampere microarchitecture was announced on May 14, 2020 . The Nvidia A100 GPU based on the Ampere architecture delivers a generational leap in accelerated computing in conjunction with CUDA 11 .
Turing cards were first released in 2018. They are the first consumer cores to launch with RTX, for raytracing, features. These are also the first consumer cards to launch with TensorCores used for matrix multiplications to accelerate convolutional neural networks. The Turing GTX line of chips do not offer RTX or TensorCores.
Pascal cards were first released in 2016.
Maxwell cards were first released in 2014.
Qualcomm offers Adreno GPUs in various types as a component of their Snapdragon SoCs. Since Adreno 300 series OpenCL support is offered.
PowerVR (Imagination Technologies) licenses IP to third parties (most notable Apple) used for system on a chip (SoC) designs. Since Series5 SGX OpenCL support via licensees is available.
Vivante licenses IP to third parties for embedded systems, the GC series offers optional OpenCL support.
- Deep Learning
- Graphics Programming
- Monte-Carlo Tree Search
- Parallel Search
- SIMD and SWAR Techniques
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- David Silver, Aja Huang, Chris J. Maddison, Arthur Guez, Laurent Sifre, George van den Driessche, Julian Schrittwieser, Ioannis Antonoglou, Veda Panneershelvam, Marc Lanctot, Sander Dieleman, Dominik Grewe, John Nham, Nal Kalchbrenner, Ilya Sutskever, Timothy Lillicrap, Madeleine Leach, Koray Kavukcuoglu, Thore Graepel, Demis Hassabis (2016). Mastering the game of Go with deep neural networks and tree search. Nature, Vol. 529 » AlphaGo
- Balázs Jákó (2016). Hardware accelerated hybrid rendering on PowerVR GPUs.  IEEE 20th Jubilee International Conference on Intelligent Engineering Systems
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- Re: Possible Board Presentation and Move Generation for GPUs by Steffan Westcott, CCC, March 20, 2011
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- Kogge Stone, Vector Based by Srdja Matovic, CCC, January 22, 2013 » Kogge-Stone Algorithm  
- GPU chess engine by Samuel Siltanen, CCC, February 27, 2013
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- GPU chess update, local memory... by Srdja Matovic, CCC, June 06, 2016
- Jetson GPU architecture by Dann Corbit, CCC, October 18, 2016 » Astro
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- Back to the basics, generating moves on gpu in parallel... by Srdja Matovic, CCC, March 05, 2017 » Move Generation
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- Chess Engine and GPU by Fishpov , Rybka Forum, October 09, 2017
- To TPU or not to TPU... by Srdja Matovic, CCC, December 16, 2017 » Deep Learning 
- Announcing lczero by Gary, CCC, January 09, 2018 » Leela Chess Zero
- GPU ANN, how to deal with host-device latencies? by Srdja Matovic, CCC, May 06, 2018 » Neural Networks
- GPU contention by Ian Kennedy, CCC, May 07, 2018 » Leela Chess Zero
- How good is the RTX 2080 Ti for Leela? by Hai, September 15, 2018 » Leela Chess Zero 
- My non-OC RTX 2070 is very fast with Lc0 by Kai Laskos, CCC, November 19, 2018 » Leela Chess Zero
- LC0 using 4 x 2080 Ti GPU's on Chess.com tourney? by M. Ansari, CCC, December 28, 2018 » Leela Chess Zero
- Generate EGTB with graphics cards? by Nguyen Pham, CCC, January 01, 2019 » Endgame Tablebases
- LCZero FAQ is missing one important fact by Jouni Uski, CCC, January 01, 2019 » Leela Chess Zero
- Michael Larabel benches lc0 on various GPUs by Warren D. Smith, LCZero Forum, January 14, 2019 » Lc0 
- Using LC0 with one or two GPUs - a guide by Srdja Matovic, CCC, March 30, 2019 » Lc0
- Wouldn't it be nice if C++ GPU by Chris Whittington, CCC, April 25, 2019 » C++
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- My home-made CUDA kernel for convolutions by Rémi Coulom, Game-AI Forum, November 09, 2019 » Deep Learning
- GPU rumors 2020 by Srdja Matovic, CCC, November 13, 2019
- AB search with NN on GPU... by Srdja Matovic, CCC, August 13, 2020 » Neural Networks 
- I stumbled upon this article on the new Nvidia RTX GPUs by Kai Laskos, CCC, September 10, 2020
- Will AMD RDNA2 based Radeon RX 6000 series kick butt with Lc0? by Srdja Matovic, CCC, November 01, 2020
- Zeta with NNUE on GPU? by Srdja Matovic, CCC, March 31, 2021 » Zeta, NNUE
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- Fast perft on GPU (upto 20 Billion nps w/o hashing) by Ankan Banerjee, CCC, June 22, 2013