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AVX2
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=Applications=
With an appropriate [[Quad-Bitboards|quad-bitboard]] class, one may generate attacks of up to four different [[Direction|directions]] using [[AVX2#IndividualShifts|individual shifts]], for instance [[Knight Pattern#Calculation|knight attacks]] or [[Sliding Piece Attacks#Multiple|sliding piece attacks]] with [[Dumb7Fill]] to generate all [[On an empty Board#PositiveRays|positive]] or [[On an empty Board#NegativeRays|negative sliding ray attacks]] passing two times orthogonal and diagonal sliding pieces.
<span id="KnightAttacks"></span>
==Knight Attacks==
=See also=
* [[CFish#AVX2 Attacks|CFish - AVX2 Attacks]]
* [[DirGolem]]
* [[NNUE]]
* [[Pigeon]]
* [[SIMD and SWAR Techniques]]
=SIMD=
* [[AltiVec]]
* [[AVX]]
* [[AVX-512]]
* [[BMI2]]
* [[MMX]]
* [[SSE]]
* [[SSE2]]
* [[Wojciech Muła]], [http://dblp.uni-trier.de/pers/hd/k/Kurz:Nathan Nathan Kurz], [https://github.com/lemire Daniel Lemire] ('''2016'''). ''Faster Population Counts Using AVX2 Instructions''. [https://arxiv.org/abs/1611.07612 arXiv:1611.07612] <ref>[https://github.com/WojciechMula/sse-popcount/blob/master/popcnt-avx512-harley-seal.cpp sse-popcount/popcnt-avx512-harley-seal.cpp at master · WojciechMula/sse-popcount · GitHub]</ref> » [[AVX-512]], [[Population Count]]
* [[Wojciech Muła]], [https://github.com/lemire Daniel Lemire] ('''2017'''). ''Faster Base64 Encoding and Decoding Using AVX2 Instructions''. [https://arxiv.org/abs/1704.00605 arXiv:1704.00605] » [https://en.wikipedia.org/wiki/Base64 Base64]
* [https://os.itec.kit.edu/21_3247.php Mathias Gottschlag], [https://os.itec.kit.edu/21_31.php Frank Bellosa] ('''2018'''). ''[https://os.itec.kit.edu/21_3486.php Mechanism to Mitigate AVX-Induced Frequency Reduction]''. [https://arxiv.org/abs/1901.04982 arXiv:1901.04982]
* [https://os.itec.kit.edu/21_3247.php Mathias Gottschlag], [https://os.itec.kit.edu/97_3742.php Philipp Machauer], [https://os.itec.kit.edu/21_3571.php Yussuf Khalil], [https://os.itec.kit.edu/21_31.php Frank Bellosa] ('''2021'''). ''[https://www.usenix.org/conference/atc21/presentation/gottschlag Fair Scheduling for AVX2 and AVX-512 Workloads]''. [https://www.usenix.org/conference/atc21 USENIX ATC '21]
=Manuals=
* [https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf Intel® Architecture Instruction Set Extensions Programming Reference] (pdf)
* [https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf Intel® 64 and IA-32 Architectures Optimization Reference Manual] (pdf)
=Forum Posts=
* [https://stackoverflow.com/questions/30330013/does-hyperthreading-have-trouble-with-avx Does Hyperthreading have trouble with AVX?] by cmylin, [https://en.wikipedia.org/wiki/Stack_Overflow Stack Overflow], May 19, 2015 » [[Thread]]
* [http://www.talkchess.com/forum3/viewtopic.php?t=65466&start=7 Re: Tapered Eval between 4 phases] by [[Youri Matiounine]], [[CCC]], October 16, 2017 » [[Tapered Eval]]
* [http://www.talkchess.com/forum3/viewtopic.php?f=7&t=67432&start=12 Re: Ryzen 2 and BMI2?] by [[Joost Buijs]], [[CCC]], May 18, 2020 » [[AMD]], [[BMI2]]
* [http://www.talkchess.com/forum3/viewtopic.php?f=2&t=75008 AVX2 optimized SF+NNUE and processor temperature] by corres, [[CCC]], September 05, 2020 » [[Stockfish NNUE]]
* [https://www.talkchess.com/forum3/viewtopic.php?f=2&t=78588 Regarding AVX2] by [[Ed Schroder|Rebel]], [[CCC]], November 03, 2021 » [[NNUE]]
=External Links=
=References=
<references />
'''[[x86|Up one Level]]'''
