SSE

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SSE (Streaming SIMD Extensions), were introduced by Intel in 1999 in their Pentium III series of processors. SSE provides an instruction set on eight 128-bit xmm registers xmm0..xmm7, with x86-64 expanded to 16 registers xmm0..xmm15, keeping vectors of four floats. Further, as a reply to AMD's [https://en.wikipedia.org/wiki/3DNow! 3DNow!], SSE introduced a few integer instructions extending the MMX instruction set.

=SSE2= The SSE2 instruction set as major enhancement to SSE, offers a more orthogonal set of instructions with vectors of four floats or two doubles, as well as integer vectors of 16 bytes, eight words, four double words or two quad words.

=See also=
 * AltiVec
 * AVX
 * AVX2
 * AVX-512
 * MMX
 * SIMD and SWAR Techniques
 * SSE2
 * SSE3
 * SSSE3
 * SSE4
 * SSE5
 * XOP

=Forum Posts=
 * planning a SSE-optimized chess engine by Aart Bik, CCC, January 12, 2005
 * advanced tapered evalutation by Marco Belli, CCC, August 08, 2014 » Tapered Eval

=External Links=
 * Streaming SIMD Extensions From Wikipedia
 * MSDN - Streaming SIMD Extensions (SSE)
 * MSDN - Integer Intrinsics Using Streaming SIMD Extensions
 * MSDN - Streaming SIMD Extensions Supported by 3DNow!
 * MSDN - Streaming SIMD Extensions that Support the Cache
 * SSE SSE2 and SSE3 for GNU C++ - Stack Overflow
 * Intel Intrinsics Guide
 * The Software Vectorization HandBook by Aart Bik

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