X86

Home * Hardware * x86



x86, referring the IA-32 architecture of the 32-bit instruction set of the Intel 80386 processor released in 1985 - the successor of Intel's 16-bit 8086 until 80286 processors. x86-32 could address up to 4GByte physical memory, had virtual memory pages and a mode to protect them over process boundaries - a requirement for multitasking operating systems, despite 16-bit MS-DOS was still popular. While the initial x86 was Complex Instruction Set Computing (CISC), the RISC versus CISC issue had become indistinct with more recent x86 processors, internally processing RISC like micro opcode. Over the time, modern architectural features, such as Out-of-order execution, Pipelining, Register Renaming and Branch Predication became an issue. 80386 was once clocked by about 25MHz. The RAM access speed could not keep up with higher and higher clock frequency of later processors - small but faster cache memory became necessary and strategies to make them efficient, nowadays even with three cache levels with different size and speed.

see x86-64 for x86 64-bit =Computer Chess= A lot of commercial and amateur PC chess programs, notably under the operating systems MS-DOS and later Windows and Linux, were developed for this widespread architecture, often taking advantage of 32-bit registers and new instructions, for instance bsf and btr for bitscanning 2 * 32-bit Bitboards and 32-bit Piece-Sets. Those instructions were usually not available through high level programming languages, but through Assembly language, later often as inline assembly of various high level language compilers, for instance Microsoft Visual C and the GNU C Compiler. Under the 16-bit real mode operating system MS-DOS, it was quite common in chess programming to use the unreal mode to allocate much more physical memory for the Transposition Table, the 16 bit operating system, not aware of the huge address space, could access. Other DOS programs relied on memory extenders.

=Architectures= While the 80386 represented the third microarchitecture (after 8086, 80286), 80486 and Pentium were the fourth and fifth, later called P5 microarchitecture. In 1995 with Pentium Pro, Intel introduced the P6 microarchitecture, eventually revived in the Pentium M line of microprocessors and the predecessor of Intel's Core 2 microarchitecture. Intel's NetBurst microarchitecture with the advent of the Pentium 4 processor, was famous for its clock speed, but no good reputation by most chess programmers, who favored the AMD K6- and K7-architecture, namely the Athlon processor at that time. To begin with the rebirth of P6 and Intel Core 2 architecture in 2006, things changed in favor to Intel again. In November 2008 the Nehalem microarchitecture appeared.

Intel's IA-64 architecture is a complete new and incompatible instruction set to IA-32. It is used by the Itanium line of processors. The backward compatible 64-bit successor was designed by AMD with the advent of Hammer or AMD64, later cloned by Intel and together referred to the x86-64 architecture.

=Register Files= x86 has eight 32-bit general purpose registers:

General Purpose
The eight general purpose registers may be treated as 32-bit Double Word, 16-bit Word and high and low Byte:

MMX
MMX was introduced with Pentium MMX in 1996, adopted by AMD's K6 in 1997. Eight 64-bit MMX-Registers: MM0 - MM7. Treated as Double or Quad Word, vector of two Floats or Double Words, and as vector if four Words or eight Bytes.

3DNow!
An MMX-floating point extension by AMD, introduced in the K6-2 processor, 1998. It uses the eight 64-bit MMX-Registers: MM0 - MM7.

SSE/SSE2
SSE was introduced by Pentium III in 1997, SSE2 by Pentium 4 in 2000 Eight 128-bit XMM-Registers: XMM0 - XMM7. Treated as vector of two Doubles (SSE) or Quad Words (SSE2), as vector of four Floats (SSE) or Double Words (SSE2), and as vector if eight Words (SSE2) or 16 Bytes (SSE2).

=CPUS=

Intel

 * 80386 1985
 * 80486 1989
 * Pentium 1993
 * Pentium MMX 1993
 * P6 microarchitecture
 * Pentium Pro 1995
 * Pentium II 1997
 * Pentium III 1999
 * NetBurst microarchitecture
 * Pentium 4 2000
 * Intel Core microarchitecture
 * Pentium M
 * Intel Atom 2008

Cyrix

 * Cyrix 6x86 1996

AMD

 * K5 March 1996
 * K6 1997
 * K6-2 1998
 * Athlon (K7) 1999
 * Athlon XP
 * Athlon MP
 * AMD has continued the name with the Athlon 64, featuring AMD64 64-bit technology, later called x86-64.

=Software=

Operating Systems

 * MS-DOS
 * Unix
 * BSD
 * Linux
 * Windows

Assembly

 * MASM
 * TASM

Pascal

 * Turbo Pascal
 * Delphi

C-Compiler

 * Turbo C
 * Borland C
 * MSVC
 * Intel-C
 * GCC

=Extensions=
 * AMX
 * AVX
 * AVX2
 * AVX-512
 * MMX
 * SSE2
 * SSE3
 * SSSE3
 * SSE4
 * SSE5
 * x86-64
 * XOP

=Manuals=

Intel

 * IA-32 Intel® Architecture Software Developer’s Manual Volume 1: Basic Architecture
 * IA-32 Intel® Architecture Software Developer’s Manual Volume 2: Instruction Set Reference
 * IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide

AMD

 * AMD Athlon Processor x86 Code Optimization Guide (pdf)

=Forum Posts=
 * Question for Eugene Nalimov by James Robertson, CCC, December 21, 1998
 * why loop unrolling isn't as useful on x86 as it once was by Wylie Garvin, CCC, February 07, 2002
 * Programmer challenge by Ed Schröder, CCC, February 20, 2003
 * Expert Assembler Question by Ed Schröder, CCC, August 26, 2005
 * Intel CPU performance-loss by security-patch?!? by Stefan Pohl, CCC, January 03, 2018

=External Links=
 * x86 from Wikipedia
 * IA-32 from Wikipedia
 * x87 from Wikipedia
 * Optimization manuals by Agner Fog
 * Agner`s CPU blog by Agner Fog
 * Microprocessor Hall of Fame from the Intel Museum
 * x86 memory segmentation from Wikipedia » Memory
 * x86 calling conventions from Wikipedia
 * 7th generation x86 CPU Comparisons by Paul Hsieh

Assembly

 * X86 Assembly/X86 Architecture from Wikibooks
 * x86 assembly language from Wikipedia » Assembly
 * x86 instruction listings from Wikipedia
 * x86 32-bit Assembly for Atheists
 * x86 Assembly Guide

Modes

 * Protected mode from Wikipedia
 * Real mode from Wikipedia
 * Unreal mode from Wikipedia
 * LOADALL from Wikipedia

Instruction Sets

 * MMX from Wikipedia
 * 3DNow! from Wikipedia
 * Streaming SIMD Extensions from Wikipedia
 * SSE2 from Wikipedia
 * Advanced Vector Extensions from Wikipedia
 * AVX-512 from Wikipedia
 * Instruction Tables (pdf) by Agner Fog
 * Advanced Matrix Extension (AMX) - x86 - WikiChip

Bugs

 * Pentium FDIV bug from Wikipedia
 * Pentium F00F bug from Wikipedia

Security Vulnerability

 * Meltdown (security vulnerability) from Wikipedia
 * Spectre (security vulnerability) from Wikipedia
 * Project Zero: Reading privileged memory with a side-channel by Jann Horn, Project Zero, January 03, 2018

=References=

Up one Level