SSE3

Home * Hardware * x86 * SSE3

SSE3 (Streaming SIMD Extensions 3), is Intel's third iteration for the SSE x86 instruction set, introduced in 2004 with the Prescott revision of the Pentium 4 CPU. In April 2005 AMD introduced a subset of SSE3 in revision E (Venice and San Diego) of their Athlon 64 CPUs. The 13 new instructions are most processing vectors of floats or doubles, most notable horizontal add and sub inside one 128-bit xmm-register, LDDQU, an alternative misaligned load, which is even quite fast for loads that cross cacheline boundaries, and FISTTP, which is a new x87 instruction.

=See also=
 * AltiVec
 * AVX
 * MMX
 * SIMD and SWAR Techniques
 * SSE
 * SSE2
 * SSSE3
 * SSE4
 * SSE5
 * x86-64
 * XOP

=Publications=
 * Daisuke Takahashi (2007). An Implementation of Parallel 1-D FFT Using SSE3 Instructions on Dual-Core Processors. Proc. Workshop on State-of-the-Art in Scientific and Parallel Computing, Lecture Notes in Computer Science, No. 4699, Springer

=External Links=
 * SSE3 from Wikipedia
 * SSE SSE2 and SSE3 for GNU C++ - Stack Overflow
 * SSEPlus Project Documentation
 * Intel Intrinsics Guide

=References=

Up one Level