Zvonko Vranesic

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Zvonko George Vranesic, a Croatian Canadian chess and correspondence chess international master, electrical engineer, and professor emeritus at Depature of Electrical and Computer Engineering, Computer Engineering Research Group, University of Toronto. His research interests covers Multiple-Valued Logic Systems, parallel computing along with NUMA, and FPGA, beside other books on that topics, along with Stephen Brown, he co-authored Fundamentals of Digital Logic with VHDL (2000) and Verilog Design.

=Chute= In the 70s, along with his student Michael Valenti, Zvonko Vranesic was co-author of Chute (CHess, University of Toronto, Engineering). He supervised Valenti's 1974 Masters Thesis, and co-authored Experiences with Chute after the WCCC 1977 in the Proceedings of the 1977 annual ACM conference.

=Chess Player= Zvonko Vranesic represented Canada at five Chess Olympiads, he scored a Grandmaster norm at the 19th Chess Olympiad in Siegen. Notable are his wins against Leonid Stein at the 16th Olympiad in Tel Aviv 1964, and versus David Levy in Lone Pine 1975.

=Selected Games=

Leonid Stein
[Event "Olympiad"] [Site "Tel Aviv (Israel)"] [Date "1964.??.??"] [Round "?"] [Result "1-0"] [White "Dr. Zvonko Vranesic"] [Black "Leonid Stein"]

1.d4 Nf6 2.c4 c5 3.d5 d6 4.Nc3 g6 5.e4 Bg7 6.Nf3 O-O 7.Be2 e6 8.O-O exd5 9.cxd5 Re8 10.Nd2 Na6 11.Re1 Nc7 12.Qc2 Rb8 13.a4 Na6 14.Bxa6 bxa6 15.Nc4 Rb4 16.Na2 Nxd5 17.Bd2 Rxc4 18.Qxc4 Nb6 19.Qc2 Qh4 20.Bc3 Bh6 21.Rad1 Nc4 22.Qe2 Be6 23.Nc1 Bf8 24.Nd3 Nb6 25.Qc2 Bd7 26.g3 Qg4 27.Nf4 Nxa4 28.Nd5 Re6 29.f3 Qg5 30.f4 Qd8 31.f5 gxf5 32.exf5 Rh6 33.Bd2 Rh5 34.Rf1 Bg7 35.Be3 Bc6 36.Qe4 Kh8 37.Qg4 Rh6 38.f6 Rxf6 39.Nxf6 Bxf6 40.Rxf6 Qxf6 41.Qc8+ Kg7 1-0

David Levy
[Event "Lone Pine"] [Site "Lone Pine"] [Date "1975.??.??"] [Round "08"] [Result "0-1"] [White "David Neil Lawrence Levy"] [Black "Dr. Zvonko Vranesic"]

1.e4 c5 2.Nf3 e6 3.d4 cxd4 4.Nxd4 Nc6 5.Nc3 d6 6.Bc4 Nf6 7.Be3 Be7 8.Qe2 a6 9.Bb3 O-O 10.O-O-O Qc7 11.Kb1 Nxd4 12.Bxd4 b5 13.e5 dxe5 14.Bxe5 Qc6 15.f3 Bb7 16.Rd4 Rfd8 17.Rhd1 Rxd4 18.Rxd4 Rd8 19.Rxd8+ Bxd8 20.Qd3 Be7 21.Qd4 Qc5 22.Ne2 Qxd4 23.Bxd4 Bd6 24.h3 e5 25.Be3 e4 26.f4 Nd5 27.Bxd5 Bxd5 28.b3 f5 29.Kb2 Kf7 30.Kc3 g6 31.Kd4 Ke6 32.Kc3 Bb7 33.Nd4+ Kd5 34.b4 Bc8 35.h4 Be7 36.g3 Bf6 37.a3 Be6 38.Bg1 h6 39.Be3 Bf7 40.Bg1 g5 41.hxg5 hxg5 42.fxg5 Be5 43.Bf2 Bg6 44.Be3 Bxg3 45.Ne2 Be5+ 46.Kb3 Bh5 0-1

=Selected Publications=

1970 ...

 * Zvonko Vranesic, E. Stewart Lee, Kenneth C. Smith (1970). A Many-Valued Algebra for Switching Systems. IEEE Transactions on Computers, Vol. 19, No. 10
 * Zvonko Vranesic, Kenneth C. Smith (1974). Engineering aspects of multi-valued logic systems. IEEE Transactions on Computers, Vol. 7, No. 9
 * Michael Valenti, Zvonko Vranesic (1977). Experiences with CHUTE. ACM conference
 * Zvonko Vranesic (1977). Multiple-Valued Logic: An Introduction and Overview. IEEE Transactions on Computers, Vol. 26, No. 12

1980 ...

 * Hussein T. Mouftah, Kenneth C. Smith, Zvonko Vranesic (1980). Ternary Rate-Multipliers. IEEE Transactions on Computers, Vol. 29, No. 10
 * Jonathan Rose, Wayne M. Loucks, Zvonko Vranesic (1985). FERMTOR: A Tunable Multiprocessor Architecture. IEEE Micro, Vol. 5, No. 4
 * Jonathan Rose, W. Martin Snelgrove, Zvonko Vranesic (1988). Parallel standard cell placement algorithms with quality equivalent to simulated annealing. IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 7, No. 3

1990 ...

 * Zeljko Zilic, Zvonko Vranesic (1993). Current-Mode CMOS Galois Field Circuits. ISMVL 1993
 * Zeljko Zilic, Zvonko Vranesic (1995). A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. IEEE Transactions on Computers, Vol. 44, No. 8
 * Zeljko Zilic, Zvonko Vranesic (1996). Using BDDs to Design ULMs for FPGAs. FPGA 1996
 * Zvonko Vranesic (1998). The FPGA Challenge. ISMVL 1998
 * Ante Grbić, Stephen Brown, Steve Caranci, Robin Grindley, Mitchell Gusat, Guy Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko Vranesic, Zeljko Zilic (1998). Design and Implementation of the NUMAchine Multiprocessor. DAC 1998, pdf
 * Stephen Brown, Zvonko Vranesic (1999). Fundamentals of Digital Logic with VHDL Design. McGraw-Hill

2000 ...

 * Robin Grindley, Tarek Abdelrahman, Stephen Brown, Steve Caranci, D. DeVries, Benjamin Gamsa, Ante Grbić, Mitchell Gusat, R. Ho, Orran Krieger, Guy Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko Vranesic, Zeljko Zilic (2000). The NUMAchine Multiprocessor. ICPP 2000, pdf
 * Valavan Manohararajah, Terry P. Borer, Stephen Brown, Zvonko Vranesic (2002). Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. FPL 2002
 * Stephen Brown, Zvonko Vranesic (2003). Fundamentals of Digital Logic with Verilog Design. McGraw-Hill
 * Valavan Manohararajah, Stephen Brown, Zvonko Vranesic (2006). Adaptive FPGAs: High-Level Architecture and a Synthesis Method. FPL 2006, pdf
 * Valavan Manohararajah, Stephen Brown, Zvonko Vranesic (2006). Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 25, No. 11
 * Stephen Brown, Zvonko Vranesic (2007). Fundamentals of Digital Logic with Verilog Design. McGraw-Hill, 2nd edition, amazon
 * Stephen Brown, Zvonko Vranesic (2008). Fundamentals of Digital Logic with VHDL Design. McGraw-Hill, 3rd edition, amazon

2010 ...

 * Franjo Plavec, Zvonko Vranesic, Stephen Brown (2013). Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs. TRETS, Vol. 6, No. 4

=External Links=
 * Zvonko Vranesic from Wikipedia
 * Z.G. Vranesic homepage
 * Vranesic Zvonko | The Chess Federation of Canada - La Fédération Canadienne des Échecs
 * The chess games of Dr. Zvonko Vranesic from chessgames.com
 * Zvonko Vranesic Croatian-Canadian International Chess Master and Professor at the University of Toronto by Nenad N. Bach and Darko Žubrinić, CROWN - Croatian World Network, July 09, 2016
 * Vranesic, Zvonko FIDE Chess Profile

=References=

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